Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

24410199

1

T1

1815

T2

530

T3

2643

full_word

8150515

1

T1

1597

T2

230

T3

2356

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32560434	1			T1	3412		T2	760		T3	4999
auto[TlIntgErrCmd]	87	1			T284	3		T285	2		T286	5
auto[TlIntgErrData]	94	1			T284	5		T285	4		T286	3
auto[TlIntgErrBoth]	99	1			T284	12		T285	4		T286	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10311007

1

T1

3069

T2

493

T3

4501

auto[1]

22249707

1

T1

343

T2

267

T3

498

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6585636	1			T1	1615		T2	381		T3	2346
auto[TlIntgErrNone]	partial	auto[1]	17824311	1			T1	200		T2	149		T3	297
auto[TlIntgErrNone]	full_word	auto[0]	3725254	1			T1	1454		T2	112		T3	2155
auto[TlIntgErrNone]	full_word	auto[1]	4425233	1			T1	143		T2	118		T3	201
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T284	1		T285	1		T286	2
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T284	1		T285	1		T286	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T284	1		T291	1		T413	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T415	1		T290	1		T418	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T284	2		T285	2		T286	2
auto[TlIntgErrData]	partial	auto[1]	41	1			T284	2		T285	2		T286	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T284	1		T291	1		T415	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T291	1		T415	1		T290	2
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T284	5		T285	2		T286	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T284	7		T285	2		T286	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T289	1		T411	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T415	1		T412	1		T413	1