Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.14	94.16	96.15	96.75		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	465736056	7508119	0	0
check_regwen_rd_A	465736056	3108	0	0
check_timeout_rd_A	465736056	2634	0	0
check_trigger_regwen_rd_A	465736056	3184	0	0
consistency_check_period_rd_A	465736056	3164	0	0
creator_sw_cfg_read_lock_rd_A	465736056	2454	0	0
direct_access_address_rd_A	465736056	2092	0	0
direct_access_wdata_0_rd_A	465736056	1419	0	0
direct_access_wdata_1_rd_A	465736056	1402	0	0
integrity_check_period_rd_A	465736056	3230	0	0
intr_enable_rd_A	465736056	4379	0	0
owner_sw_cfg_read_lock_rd_A	465736056	2343	0	0
rot_creator_auth_codesign_read_lock_rd_A	465736056	2425	0	0
rot_creator_auth_state_read_lock_rd_A	465736056	2432	0	0
vendor_test_read_lock_rd_A	465736056	2280	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465736056	7508119	0	0
T8	376776	68286	0	0
T9	755056	0	0	0
T13	269576	58299	0	0
T14	0	99091	0	0
T17	0	97342	0	0
T24	10711	0	0	0
T31	0	79764	0	0
T43	41007	0	0	0
T61	28844	0	0	0
T65	12530	0	0	0
T100	34097	0	0	0
T103	23800	0	0	0
T134	0	57198	0	0
T136	4563	0	0	0
T137	0	59737	0	0
T231	0	35732	0	0
T277	0	32461	0	0
T292	0	55360	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465736056	3108	0	0
T93	70113	0	0	0
T94	164430	0	0	0
T95	165782	0	0	0
T96	79172	0	0	0
T120	0	82	0	0
T134	284811	35	0	0
T187	22037	0	0	0
T266	0	75	0	0
T275	0	133	0	0
T277	196608	25	0	0
T278	0	92	0	0
T392	0	99	0	0
T393	0	12	0	0
T394	0	165	0	0
T395	0	12	0	0
T396	17462	0	0	0
T397	14707	0	0	0
T398	12942	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465736056	2634	0	0
T93	70113	0	0	0
T94	164430	0	0	0
T95	165782	0	0	0
T96	79172	0	0	0
T120	0	86	0	0
T134	284811	61	0	0
T187	22037	0	0	0
T266	0	76	0	0
T275	0	122	0	0
T277	196608	19	0	0
T278	0	50	0	0
T392	0	79	0	0
T393	0	28	0	0
T394	0	200	0	0
T395	0	32	0	0
T396	17462	0	0	0
T397	14707	0	0	0
T398	12942	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465736056	3184	0	0
T93	70113	0	0	0
T94	164430	0	0	0
T95	165782	0	0	0
T96	79172	0	0	0
T120	0	108	0	0
T134	284811	40	0	0
T187	22037	0	0	0
T266	0	30	0	0
T275	0	155	0	0
T277	196608	41	0	0
T278	0	67	0	0
T392	0	92	0	0
T393	0	40	0	0
T394	0	111	0	0
T395	0	25	0	0
T396	17462	0	0	0
T397	14707	0	0	0
T398	12942	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465736056	3164	0	0
T93	70113	0	0	0
T94	164430	0	0	0
T95	165782	0	0	0
T96	79172	0	0	0
T120	0	99	0	0
T134	284811	56	0	0
T187	22037	0	0	0
T266	0	90	0	0
T275	0	153	0	0
T277	196608	21	0	0
T278	0	69	0	0
T392	0	102	0	0
T393	0	27	0	0
T394	0	129	0	0
T395	0	28	0	0
T396	17462	0	0	0
T397	14707	0	0	0
T398	12942	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465736056	2454	0	0
T93	70113	0	0	0
T94	164430	0	0	0
T95	165782	0	0	0
T96	79172	0	0	0
T120	0	96	0	0
T134	284811	37	0	0
T187	22037	0	0	0
T266	0	97	0	0
T275	0	153	0	0
T277	196608	20	0	0
T278	0	87	0	0
T392	0	61	0	0
T393	0	17	0	0
T394	0	170	0	0
T395	0	31	0	0
T396	17462	0	0	0
T397	14707	0	0	0
T398	12942	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465736056	2092	0	0
T93	70113	0	0	0
T94	164430	0	0	0
T95	165782	0	0	0
T96	79172	0	0	0
T120	0	87	0	0
T134	284811	42	0	0
T187	22037	0	0	0
T266	0	87	0	0
T275	0	140	0	0
T277	196608	38	0	0
T278	0	123	0	0
T392	0	139	0	0
T393	0	33	0	0
T394	0	201	0	0
T395	0	32	0	0
T396	17462	0	0	0
T397	14707	0	0	0
T398	12942	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465736056	1419	0	0
T93	70113	0	0	0
T94	164430	0	0	0
T95	165782	0	0	0
T96	79172	0	0	0
T120	0	83	0	0
T134	284811	32	0	0
T187	22037	0	0	0
T266	0	66	0	0
T275	0	68	0	0
T277	196608	32	0	0
T278	0	70	0	0
T392	0	35	0	0
T393	0	12	0	0
T394	0	152	0	0
T395	0	3	0	0
T396	17462	0	0	0
T397	14707	0	0	0
T398	12942	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465736056	1402	0	0
T93	70113	0	0	0
T94	164430	0	0	0
T95	165782	0	0	0
T96	79172	0	0	0
T120	0	77	0	0
T134	284811	23	0	0
T187	22037	0	0	0
T266	0	62	0	0
T275	0	134	0	0
T277	196608	10	0	0
T278	0	82	0	0
T392	0	34	0	0
T393	0	15	0	0
T394	0	128	0	0
T395	0	8	0	0
T396	17462	0	0	0
T397	14707	0	0	0
T398	12942	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465736056	3230	0	0
T93	70113	0	0	0
T94	164430	0	0	0
T95	165782	0	0	0
T96	79172	0	0	0
T120	0	52	0	0
T134	284811	34	0	0
T187	22037	0	0	0
T266	0	56	0	0
T275	0	135	0	0
T277	196608	12	0	0
T278	0	108	0	0
T392	0	128	0	0
T393	0	26	0	0
T394	0	171	0	0
T395	0	37	0	0
T396	17462	0	0	0
T397	14707	0	0	0
T398	12942	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465736056	4379	0	0
T9	755056	27	0	0
T13	269576	0	0	0
T63	0	4	0	0
T67	604340	0	0	0
T73	0	3	0	0
T103	23800	0	0	0
T104	10510	0	0	0
T105	23073	0	0	0
T118	11592	0	0	0
T134	0	50	0	0
T149	85187	0	0	0
T153	17368	0	0	0
T184	12486	0	0	0
T266	0	98	0	0
T275	0	169	0	0
T277	0	41	0	0
T278	0	136	0	0
T392	0	133	0	0
T393	0	41	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465736056	2343	0	0
T93	70113	0	0	0
T94	164430	0	0	0
T95	165782	0	0	0
T96	79172	0	0	0
T120	0	98	0	0
T134	284811	29	0	0
T187	22037	0	0	0
T266	0	55	0	0
T275	0	168	0	0
T277	196608	17	0	0
T278	0	30	0	0
T392	0	110	0	0
T393	0	21	0	0
T394	0	150	0	0
T395	0	26	0	0
T396	17462	0	0	0
T397	14707	0	0	0
T398	12942	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465736056	2425	0	0
T93	70113	0	0	0
T94	164430	0	0	0
T95	165782	0	0	0
T96	79172	0	0	0
T120	0	106	0	0
T134	284811	53	0	0
T187	22037	0	0	0
T266	0	60	0	0
T275	0	169	0	0
T277	196608	32	0	0
T278	0	115	0	0
T392	0	80	0	0
T393	0	61	0	0
T394	0	191	0	0
T395	0	37	0	0
T396	17462	0	0	0
T397	14707	0	0	0
T398	12942	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465736056	2432	0	0
T93	70113	0	0	0
T94	164430	0	0	0
T95	165782	0	0	0
T96	79172	0	0	0
T120	0	76	0	0
T134	284811	38	0	0
T187	22037	0	0	0
T266	0	97	0	0
T275	0	162	0	0
T277	196608	31	0	0
T278	0	85	0	0
T392	0	115	0	0
T393	0	31	0	0
T394	0	103	0	0
T395	0	42	0	0
T396	17462	0	0	0
T397	14707	0	0	0
T398	12942	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465736056	2280	0	0
T93	70113	0	0	0
T94	164430	0	0	0
T95	165782	0	0	0
T96	79172	0	0	0
T120	0	84	0	0
T134	284811	18	0	0
T187	22037	0	0	0
T266	0	37	0	0
T275	0	148	0	0
T277	196608	31	0	0
T278	0	100	0	0
T392	0	147	0	0
T393	0	16	0	0
T394	0	155	0	0
T395	0	18	0	0
T396	17462	0	0	0
T397	14707	0	0	0
T398	12942	0	0	0