Line Coverage for Module :
prim_sync_reqack_data
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 0 | 0 | |
CONT_ASSIGN | 156 | 0 | 0 | |
ALWAYS | 159 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
93 |
1 |
1 |
153 |
|
unreachable |
156 |
|
unreachable |
159 |
|
unreachable |
160 |
|
unreachable |
162 |
|
unreachable |
Assert Coverage for Module :
prim_sync_reqack_data
Assertion Details
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462772914 |
607551 |
0 |
0 |
T4 |
74889 |
1118 |
0 |
0 |
T5 |
678672 |
6418 |
0 |
0 |
T6 |
165586 |
546 |
0 |
0 |
T7 |
117076 |
0 |
0 |
0 |
T8 |
376776 |
1561 |
0 |
0 |
T9 |
0 |
3442 |
0 |
0 |
T10 |
15102 |
0 |
0 |
0 |
T11 |
9871 |
0 |
0 |
0 |
T12 |
120257 |
0 |
0 |
0 |
T13 |
0 |
2660 |
0 |
0 |
T24 |
10711 |
0 |
0 |
0 |
T43 |
0 |
190 |
0 |
0 |
T100 |
34097 |
0 |
0 |
0 |
T103 |
0 |
270 |
0 |
0 |
T105 |
0 |
190 |
0 |
0 |
T149 |
0 |
742 |
0 |
0 |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
462772914 |
607465 |
0 |
0 |
T4 |
74889 |
1118 |
0 |
0 |
T5 |
678672 |
6417 |
0 |
0 |
T6 |
165586 |
546 |
0 |
0 |
T7 |
117076 |
0 |
0 |
0 |
T8 |
376776 |
1561 |
0 |
0 |
T9 |
0 |
3442 |
0 |
0 |
T10 |
15102 |
0 |
0 |
0 |
T11 |
9871 |
0 |
0 |
0 |
T12 |
120257 |
0 |
0 |
0 |
T13 |
0 |
2660 |
0 |
0 |
T24 |
10711 |
0 |
0 |
0 |
T43 |
0 |
190 |
0 |
0 |
T100 |
34097 |
0 |
0 |
0 |
T103 |
0 |
270 |
0 |
0 |
T105 |
0 |
190 |
0 |
0 |
T149 |
0 |
742 |
0 |
0 |