Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.33 100.00 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.00 100.00 100.00 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.23 100.00 100.00 85.00 100.00 96.15 gen_partitions[0].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
u_prim_secded_inv_72_64_enc 100.00 100.00



Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.33 100.00 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.00 100.00 100.00 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 100.00 91.67 100.00 100.00 gen_partitions[1].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
u_prim_secded_inv_72_64_enc 100.00 100.00



Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.33 100.00 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.00 100.00 100.00 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.75 100.00 97.06 91.67 100.00 100.00 gen_partitions[2].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
u_prim_secded_inv_72_64_enc 100.00 100.00



Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.33 100.00 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.00 100.00 100.00 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 100.00 91.67 100.00 100.00 gen_partitions[3].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
u_prim_secded_inv_72_64_enc 100.00 100.00



Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.33 100.00 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.00 100.00 100.00 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 100.00 91.67 100.00 100.00 gen_partitions[4].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
u_prim_secded_inv_72_64_enc 100.00 100.00



Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.62 97.64 95.24 96.00 96.36 82.86 gen_partitions[5].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
u_prim_secded_inv_72_64_enc 100.00 100.00



Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.75 95.45 92.86 91.67 90.91 82.86 gen_partitions[6].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
u_prim_secded_inv_72_64_enc 100.00 100.00



Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.65 98.00 93.75 91.67 95.38 94.44 gen_partitions[7].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
u_prim_secded_inv_72_64_enc 100.00 100.00



Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 96.00 93.75 91.67 93.85 94.44 gen_partitions[8].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 100.00 100.00
u_prim_secded_inv_72_64_enc 100.00 100.00



Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.20 98.00 93.75 94.44 95.38 94.44 gen_partitions[9].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 100.00 100.00
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 100.00 100.00
u_prim_secded_inv_72_64_enc 100.00 100.00



Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.92 100.00 75.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.90 96.91 100.00 95.24 100.00 82.35 gen_partitions[10].gen_lifecycle.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec 75.00 75.00
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec 75.74 75.74
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec 77.94 77.94
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec 82.35 82.35
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec 68.38 68.38
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec 77.94 77.94
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec 76.47 76.47
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec 72.06 72.06
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec 69.12 69.12
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec 63.24 63.24
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec 69.85 69.85
u_prim_secded_inv_72_64_enc 100.00 100.00

Line Coverage for Module : otp_ctrl_ecc_reg ( parameter Width=64,Depth=9,Aw=4,EccWidth=8 + Width=64,Depth=2,Aw=1,EccWidth=8 + Width=64,Depth=5,Aw=3,EccWidth=8 + Width=64,Depth=11,Aw=4,EccWidth=8 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORELINE
100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORELINE
100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORELINE
100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORELINE
100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORELINE
100.00 100.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6088100.00
CONT_ASSIGN8711100.00
ALWAYS9055100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
61 1 1
62 1 1
64 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
MISSING_ELSE
87 1 1
90 1 1
91 1 1
92 1 1
94 1 1
95 1 1


Line Coverage for Module : otp_ctrl_ecc_reg ( parameter Width=64,Depth=1,Aw=1,EccWidth=8 )
Line Coverage for Module self-instances :
SCORELINE
93.33 100.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORELINE
93.33 100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORELINE
93.33 100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORELINE
93.33 100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORELINE
93.33 100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS4688100.00
CONT_ASSIGN8711100.00
ALWAYS9055100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
47 1 1
48 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
MISSING_ELSE
==> MISSING_ELSE
87 1 1
90 1 1
91 1 1
92 1 1
94 1 1
95 1 1


Branch Coverage for Module : otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 90 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 90 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((32'(addr_i) < Depth)) -2-: 67 if (wren_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T25


Assert Coverage for Module : otp_ctrl_ecc_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 2147483647 0 0
DataOutKnown_A 2147483647 2147483647 0 0
EccErrKnown_A 2147483647 2147483647 0 0
EccKnown_A 2147483647 2147483647 0 0
RDataOutKnown_A 2147483647 2147483647 0 0
WidthMustBe64bit_A 12705 12705 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 151041 148159 0 0
T2 168916 165913 0 0
T3 202103 199188 0 0
T4 823779 806113 0 0
T5 7465392 7348077 0 0
T6 1821446 1808422 0 0
T7 1287836 1284943 0 0
T10 166122 163449 0 0
T11 108581 106392 0 0
T12 1322827 1319109 0 0

DataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 151041 148159 0 0
T2 168916 165913 0 0
T3 202103 199188 0 0
T4 823779 806113 0 0
T5 7465392 7348077 0 0
T6 1821446 1808422 0 0
T7 1287836 1284943 0 0
T10 166122 163449 0 0
T11 108581 106392 0 0
T12 1322827 1319109 0 0

EccErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 151041 148159 0 0
T2 168916 165913 0 0
T3 202103 199188 0 0
T4 823779 806113 0 0
T5 7465392 7348077 0 0
T6 1821446 1808422 0 0
T7 1287836 1284943 0 0
T10 166122 163449 0 0
T11 108581 106392 0 0
T12 1322827 1319109 0 0

EccKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 151041 148159 0 0
T2 168916 165913 0 0
T3 202103 199188 0 0
T4 823779 806113 0 0
T5 7465392 7348077 0 0
T6 1821446 1808422 0 0
T7 1287836 1284943 0 0
T10 166122 163449 0 0
T11 108581 106392 0 0
T12 1322827 1319109 0 0

RDataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 151041 148159 0 0
T2 168916 165913 0 0
T3 202103 199188 0 0
T4 823779 806113 0 0
T5 7465392 7348077 0 0
T6 1821446 1808422 0 0
T7 1287836 1284943 0 0
T10 166122 163449 0 0
T11 108581 106392 0 0
T12 1322827 1319109 0 0

WidthMustBe64bit_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12705 12705 0 0
T1 11 11 0 0
T2 11 11 0 0
T3 11 11 0 0
T4 11 11 0 0
T5 11 11 0 0
T6 11 11 0 0
T7 11 11 0 0
T10 11 11 0 0
T11 11 11 0 0
T12 11 11 0 0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS4688100.00
CONT_ASSIGN8711100.00
ALWAYS9055100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
47 1 1
48 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
MISSING_ELSE
==> MISSING_ELSE
87 1 1
90 1 1
91 1 1
92 1 1
94 1 1
95 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 90 2 2 100.00
IF 65 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 90 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((32'(addr_i) < Depth)) -2-: 67 if (wren_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Not Covered


Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 462772914 461830240 0 0
DataOutKnown_A 462772914 461830240 0 0
EccErrKnown_A 462772914 461830240 0 0
EccKnown_A 462772914 461830240 0 0
RDataOutKnown_A 462772914 461830240 0 0
WidthMustBe64bit_A 1155 1155 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

DataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

RDataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

WidthMustBe64bit_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1155 1155 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS4688100.00
CONT_ASSIGN8711100.00
ALWAYS9055100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
47 1 1
48 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
MISSING_ELSE
==> MISSING_ELSE
87 1 1
90 1 1
91 1 1
92 1 1
94 1 1
95 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 90 2 2 100.00
IF 65 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 90 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((32'(addr_i) < Depth)) -2-: 67 if (wren_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Not Covered


Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 462772914 461830240 0 0
DataOutKnown_A 462772914 461830240 0 0
EccErrKnown_A 462772914 461830240 0 0
EccKnown_A 462772914 461830240 0 0
RDataOutKnown_A 462772914 461830240 0 0
WidthMustBe64bit_A 1155 1155 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

DataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

RDataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

WidthMustBe64bit_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1155 1155 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS4688100.00
CONT_ASSIGN8711100.00
ALWAYS9055100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
47 1 1
48 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
MISSING_ELSE
==> MISSING_ELSE
87 1 1
90 1 1
91 1 1
92 1 1
94 1 1
95 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 90 2 2 100.00
IF 65 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 90 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((32'(addr_i) < Depth)) -2-: 67 if (wren_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Not Covered


Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 462772914 461830240 0 0
DataOutKnown_A 462772914 461830240 0 0
EccErrKnown_A 462772914 461830240 0 0
EccKnown_A 462772914 461830240 0 0
RDataOutKnown_A 462772914 461830240 0 0
WidthMustBe64bit_A 1155 1155 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

DataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

RDataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

WidthMustBe64bit_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1155 1155 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS4688100.00
CONT_ASSIGN8711100.00
ALWAYS9055100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
47 1 1
48 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
MISSING_ELSE
==> MISSING_ELSE
87 1 1
90 1 1
91 1 1
92 1 1
94 1 1
95 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 90 2 2 100.00
IF 65 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 90 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((32'(addr_i) < Depth)) -2-: 67 if (wren_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Not Covered


Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 462772914 461830240 0 0
DataOutKnown_A 462772914 461830240 0 0
EccErrKnown_A 462772914 461830240 0 0
EccKnown_A 462772914 461830240 0 0
RDataOutKnown_A 462772914 461830240 0 0
WidthMustBe64bit_A 1155 1155 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

DataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

RDataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

WidthMustBe64bit_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1155 1155 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS4688100.00
CONT_ASSIGN8711100.00
ALWAYS9055100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
46 1 1
47 1 1
48 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
MISSING_ELSE
==> MISSING_ELSE
87 1 1
90 1 1
91 1 1
92 1 1
94 1 1
95 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 90 2 2 100.00
IF 65 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 90 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((32'(addr_i) < Depth)) -2-: 67 if (wren_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Not Covered


Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 462772914 461830240 0 0
DataOutKnown_A 462772914 461830240 0 0
EccErrKnown_A 462772914 461830240 0 0
EccKnown_A 462772914 461830240 0 0
RDataOutKnown_A 462772914 461830240 0 0
WidthMustBe64bit_A 1155 1155 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

DataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

RDataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

WidthMustBe64bit_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1155 1155 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6088100.00
CONT_ASSIGN8711100.00
ALWAYS9055100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
61 1 1
62 1 1
64 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
MISSING_ELSE
87 1 1
90 1 1
91 1 1
92 1 1
94 1 1
95 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 90 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 90 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((32'(addr_i) < Depth)) -2-: 67 if (wren_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T25


Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 462772914 461830240 0 0
DataOutKnown_A 462772914 461830240 0 0
EccErrKnown_A 462772914 461830240 0 0
EccKnown_A 462772914 461830240 0 0
RDataOutKnown_A 462772914 461830240 0 0
WidthMustBe64bit_A 1155 1155 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

DataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

RDataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

WidthMustBe64bit_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1155 1155 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6088100.00
CONT_ASSIGN8711100.00
ALWAYS9055100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
61 1 1
62 1 1
64 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
==> MISSING_ELSE
87 1 1
90 1 1
91 1 1
92 1 1
94 1 1
95 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 90 2 2 100.00
IF 65 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 90 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((32'(addr_i) < Depth)) -2-: 67 if (wren_i)

Branches:
-1--2-StatusTestsExclude Annotation
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Excluded VC_COV_UNR


Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 462772914 461830240 0 0
DataOutKnown_A 462772914 461830240 0 0
EccErrKnown_A 462772914 461830240 0 0
EccKnown_A 462772914 461830240 0 0
RDataOutKnown_A 462772914 461830240 0 0
WidthMustBe64bit_A 1155 1155 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

DataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

RDataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

WidthMustBe64bit_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1155 1155 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6088100.00
CONT_ASSIGN8711100.00
ALWAYS9055100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
61 1 1
62 1 1
64 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
MISSING_ELSE
87 1 1
90 1 1
91 1 1
92 1 1
94 1 1
95 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 90 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 90 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((32'(addr_i) < Depth)) -2-: 67 if (wren_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T25


Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 462772914 461830240 0 0
DataOutKnown_A 462772914 461830240 0 0
EccErrKnown_A 462772914 461830240 0 0
EccKnown_A 462772914 461830240 0 0
RDataOutKnown_A 462772914 461830240 0 0
WidthMustBe64bit_A 1155 1155 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

DataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

RDataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

WidthMustBe64bit_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1155 1155 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6088100.00
CONT_ASSIGN8711100.00
ALWAYS9055100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
61 1 1
62 1 1
64 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
MISSING_ELSE
87 1 1
90 1 1
91 1 1
92 1 1
94 1 1
95 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 90 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 90 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((32'(addr_i) < Depth)) -2-: 67 if (wren_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T25


Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 462772914 461830240 0 0
DataOutKnown_A 462772914 461830240 0 0
EccErrKnown_A 462772914 461830240 0 0
EccKnown_A 462772914 461830240 0 0
RDataOutKnown_A 462772914 461830240 0 0
WidthMustBe64bit_A 1155 1155 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

DataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

RDataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

WidthMustBe64bit_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1155 1155 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6088100.00
CONT_ASSIGN8711100.00
ALWAYS9055100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
61 1 1
62 1 1
64 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
MISSING_ELSE
87 1 1
90 1 1
91 1 1
92 1 1
94 1 1
95 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 90 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 90 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((32'(addr_i) < Depth)) -2-: 67 if (wren_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T25


Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 462772914 461830240 0 0
DataOutKnown_A 462772914 461830240 0 0
EccErrKnown_A 462772914 461830240 0 0
EccKnown_A 462772914 461830240 0 0
RDataOutKnown_A 462772914 461830240 0 0
WidthMustBe64bit_A 1155 1155 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

DataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

RDataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

WidthMustBe64bit_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1155 1155 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

Line Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6088100.00
CONT_ASSIGN8711100.00
ALWAYS9055100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
61 1 1
62 1 1
64 1 1
65 1 1
66 1 1
67 1 1
68 1 1
MISSING_ELSE
MISSING_ELSE
87 1 1
90 1 1
91 1 1
92 1 1
94 1 1
95 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 90 2 2 100.00
IF 65 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 90 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 65 if ((32'(addr_i) < Depth)) -2-: 67 if (wren_i)

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T25


Assert Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 462772914 461830240 0 0
DataOutKnown_A 462772914 461830240 0 0
EccErrKnown_A 462772914 461830240 0 0
EccKnown_A 462772914 461830240 0 0
RDataOutKnown_A 462772914 461830240 0 0
WidthMustBe64bit_A 1155 1155 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

DataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

EccKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

RDataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 462772914 461830240 0 0
T1 13731 13469 0 0
T2 15356 15083 0 0
T3 18373 18108 0 0
T4 74889 73283 0 0
T5 678672 668007 0 0
T6 165586 164402 0 0
T7 117076 116813 0 0
T10 15102 14859 0 0
T11 9871 9672 0 0
T12 120257 119919 0 0

WidthMustBe64bit_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1155 1155 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%