Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.36	65.65	89.08			88.89	53.85

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_part_sel_idx	74.55	65.65	89.83			88.89	53.85
tb.dut.u_otp_ctrl_dai.u_part_sel_idx	74.55	65.65	89.83			88.89	53.85

---

Module Instance : tb.dut.u_part_sel_idx

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.55	65.65	89.83			88.89	53.85

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.55	65.65	89.83			88.89	53.85

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.14	94.16	96.15	96.75		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp_ctrl_dai.u_part_sel_idx

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.55	65.65	89.83			88.89	53.85

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.55	65.65	89.83			88.89	53.85

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.73	95.88	95.06		87.72	90.00	100.00	u_otp_ctrl_dai

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		131	86	65.65
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	97	1	0	0.00
CONT_ASSIGN	97	1	0	0.00
CONT_ASSIGN	97	1	0	0.00
CONT_ASSIGN	97	1	0	0.00
CONT_ASSIGN	97	1	0	0.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	0	0.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	0	0.00
ALWAYS	105	6	0	0.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	11	11
87	0	11
89	0	11
97	0	5
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	0	1
107	0	1
109	0	1
110	0	1
112	0	1
113	0	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	0	1
107	0	1
109	0	1
110	0	1
112	0	1
113	0	1
105	0	1
107	0	1
109	0	1
110	0	1
112	0	1
113	0	1
124	1	1
128	1	1
129	1	1
132		unreachable

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	119	106	89.08
Logical	119	106	89.08
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T4

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Unreachable

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[3].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[3].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[4].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[4].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T7,T8,T9

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Unreachable

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[7].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[7].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Unreachable

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[3].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[4].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[7].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[3].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[4].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[7].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[7].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[7].Pa] & gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Unreachable

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		54	48	88.89
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	1	0	0.00
TERNARY	110	1	0	0.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	1	0	0.00
TERNARY	110	1	0	0.00
TERNARY	109	1	0	0.00
TERNARY	110	1	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	7	53.85
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	7	53.85

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	925545828	923660480	0	0
CheckNGreaterZero_A	2310	2310	0	0
GntImpliesReady_A	925545828	0	0	0
GntImpliesValid_A	925545828	0	0	0
GrantKnown_A	925545828	923660480	0	0
IdxKnown_A	925545828	923660480	0	0
IndexIsCorrect_A	925545828	0	0	0
NoReadyValidNoGrant_A	925545828	0	0	0
Priority_A	925545828	923660480	0	0
ReadyAndValidImplyGrant_A	925545828	0	0	0
ReqAndReadyImplyGrant_A	925545828	0	0	0
ReqImpliesValid_A	925545828	923660480	0	0
ValidKnown_A	925545828	923660480	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925545828	923660480	0	0
T1	27462	26938	0	0
T2	30712	30166	0	0
T3	36746	36216	0	0
T4	149778	146566	0	0
T5	1357344	1336014	0	0
T6	331172	328804	0	0
T7	234152	233626	0	0
T10	30204	29718	0	0
T11	19742	19344	0	0
T12	240514	239838	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2310	2310	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T10	2	2	0	0
T11	2	2	0	0
T12	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925545828	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925545828	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925545828	923660480	0	0
T1	27462	26938	0	0
T2	30712	30166	0	0
T3	36746	36216	0	0
T4	149778	146566	0	0
T5	1357344	1336014	0	0
T6	331172	328804	0	0
T7	234152	233626	0	0
T10	30204	29718	0	0
T11	19742	19344	0	0
T12	240514	239838	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925545828	923660480	0	0
T1	27462	26938	0	0
T2	30712	30166	0	0
T3	36746	36216	0	0
T4	149778	146566	0	0
T5	1357344	1336014	0	0
T6	331172	328804	0	0
T7	234152	233626	0	0
T10	30204	29718	0	0
T11	19742	19344	0	0
T12	240514	239838	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925545828	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925545828	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925545828	923660480	0	0
T1	27462	26938	0	0
T2	30712	30166	0	0
T3	36746	36216	0	0
T4	149778	146566	0	0
T5	1357344	1336014	0	0
T6	331172	328804	0	0
T7	234152	233626	0	0
T10	30204	29718	0	0
T11	19742	19344	0	0
T12	240514	239838	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925545828	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925545828	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925545828	923660480	0	0
T1	27462	26938	0	0
T2	30712	30166	0	0
T3	36746	36216	0	0
T4	149778	146566	0	0
T5	1357344	1336014	0	0
T6	331172	328804	0	0
T7	234152	233626	0	0
T10	30204	29718	0	0
T11	19742	19344	0	0
T12	240514	239838	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925545828	923660480	0	0
T1	27462	26938	0	0
T2	30712	30166	0	0
T3	36746	36216	0	0
T4	149778	146566	0	0
T5	1357344	1336014	0	0
T6	331172	328804	0	0
T7	234152	233626	0	0
T10	30204	29718	0	0
T11	19742	19344	0	0
T12	240514	239838	0	0

Line Coverage for Instance : tb.dut.u_part_sel_idx

	Line No.	Total	Covered	Percent
TOTAL		131	86	65.65
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	97	1	0	0.00
CONT_ASSIGN	97	1	0	0.00
CONT_ASSIGN	97	1	0	0.00
CONT_ASSIGN	97	1	0	0.00
CONT_ASSIGN	97	1	0	0.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	0	0.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	0	0.00
ALWAYS	105	6	0	0.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	11	11
87	0	11
89	0	11
97	0	5
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	0	1
107	0	1
109	0	1
110	0	1
112	0	1
113	0	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	0	1
107	0	1
109	0	1
110	0	1
112	0	1
113	0	1
105	0	1
107	0	1
109	0	1
110	0	1
112	0	1
113	0	1
124	1	1
128	1	1
129	1	1
132		unreachable

---

Cond Coverage for Instance : tb.dut.u_part_sel_idx

	Total	Covered	Percent
Conditions	118	106	89.83
Logical	118	106	89.83
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Excluded		vcs_gen_start:level=0,offset=0:vcs_gen_end:VC_COV_UNR
0	1	Covered	T8,T13,T14
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T14
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T8,T13,T14

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T13,T14
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T13,T14
1	0	Covered	T8,T13,T14

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Unreachable

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T13,T14
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[3].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[3].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T13,T14
1	0	Covered	T8,T13,T14

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[4].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[4].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T13,T14
1	0	Covered	T8,T13,T14

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T8,T13,T14

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Unreachable

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[7].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[7].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Unreachable

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T13,T14

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T8,T13,T14
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])

-1-	Status	Tests
0	Covered	T8,T13,T14
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[3].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])

-1-	Status	Tests
0	Covered	T8,T13,T14
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[4].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])

-1-	Status	Tests
0	Covered	T8,T13,T14
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])

-1-	Status	Tests
0	Covered	T8,T13,T14
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[7].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T13,T14

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T8,T13,T14
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])

-1-	Status	Tests
0	Covered	T8,T13,T14
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[3].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])

-1-	Status	Tests
0	Covered	T8,T13,T14
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[4].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])

-1-	Status	Tests
0	Covered	T8,T13,T14
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])

-1-	Status	Tests
0	Covered	T8,T13,T14
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[7].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T14
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T14
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T14
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T14
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T14
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[7].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T13,T14
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[7].Pa] & gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Unreachable

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_part_sel_idx

	Line No.	Total	Covered	Percent
Branches		54	48	88.89
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	1	0	0.00
TERNARY	110	1	0	0.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	1	0	0.00
TERNARY	110	1	0	0.00
TERNARY	109	1	0	0.00
TERNARY	110	1	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T13,T14

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T13,T14

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T13,T14

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T13,T14

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T13,T14

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T13,T14

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T13,T14

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T13,T14

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T13,T14

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T8,T13,T14

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

---

Assert Coverage for Instance : tb.dut.u_part_sel_idx

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	7	53.85
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	7	53.85

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	462772914	461830240	0	0
CheckNGreaterZero_A	1155	1155	0	0
GntImpliesReady_A	462772914	0	0	0
GntImpliesValid_A	462772914	0	0	0
GrantKnown_A	462772914	461830240	0	0
IdxKnown_A	462772914	461830240	0	0
IndexIsCorrect_A	462772914	0	0	0
NoReadyValidNoGrant_A	462772914	0	0	0
Priority_A	462772914	461830240	0	0
ReadyAndValidImplyGrant_A	462772914	0	0	0
ReqAndReadyImplyGrant_A	462772914	0	0	0
ReqImpliesValid_A	462772914	461830240	0	0
ValidKnown_A	462772914	461830240	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	461830240	0	0
T1	13731	13469	0	0
T2	15356	15083	0	0
T3	18373	18108	0	0
T4	74889	73283	0	0
T5	678672	668007	0	0
T6	165586	164402	0	0
T7	117076	116813	0	0
T10	15102	14859	0	0
T11	9871	9672	0	0
T12	120257	119919	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	461830240	0	0
T1	13731	13469	0	0
T2	15356	15083	0	0
T3	18373	18108	0	0
T4	74889	73283	0	0
T5	678672	668007	0	0
T6	165586	164402	0	0
T7	117076	116813	0	0
T10	15102	14859	0	0
T11	9871	9672	0	0
T12	120257	119919	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	461830240	0	0
T1	13731	13469	0	0
T2	15356	15083	0	0
T3	18373	18108	0	0
T4	74889	73283	0	0
T5	678672	668007	0	0
T6	165586	164402	0	0
T7	117076	116813	0	0
T10	15102	14859	0	0
T11	9871	9672	0	0
T12	120257	119919	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	461830240	0	0
T1	13731	13469	0	0
T2	15356	15083	0	0
T3	18373	18108	0	0
T4	74889	73283	0	0
T5	678672	668007	0	0
T6	165586	164402	0	0
T7	117076	116813	0	0
T10	15102	14859	0	0
T11	9871	9672	0	0
T12	120257	119919	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	461830240	0	0
T1	13731	13469	0	0
T2	15356	15083	0	0
T3	18373	18108	0	0
T4	74889	73283	0	0
T5	678672	668007	0	0
T6	165586	164402	0	0
T7	117076	116813	0	0
T10	15102	14859	0	0
T11	9871	9672	0	0
T12	120257	119919	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	461830240	0	0
T1	13731	13469	0	0
T2	15356	15083	0	0
T3	18373	18108	0	0
T4	74889	73283	0	0
T5	678672	668007	0	0
T6	165586	164402	0	0
T7	117076	116813	0	0
T10	15102	14859	0	0
T11	9871	9672	0	0
T12	120257	119919	0	0

Line Coverage for Instance : tb.dut.u_otp_ctrl_dai.u_part_sel_idx

	Line No.	Total	Covered	Percent
TOTAL		131	86	65.65
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	97	1	0	0.00
CONT_ASSIGN	97	1	0	0.00
CONT_ASSIGN	97	1	0	0.00
CONT_ASSIGN	97	1	0	0.00
CONT_ASSIGN	97	1	0	0.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	0	0.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	6	100.00
ALWAYS	105	6	0	0.00
ALWAYS	105	6	0	0.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	11	11
87	0	11
89	0	11
97	0	5
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	0	1
107	0	1
109	0	1
110	0	1
112	0	1
113	0	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
105	0	1
107	0	1
109	0	1
110	0	1
112	0	1
113	0	1
105	0	1
107	0	1
109	0	1
110	0	1
112	0	1
113	0	1
124	1	1
128	1	1
129	1	1
132		unreachable

---

Cond Coverage for Instance : tb.dut.u_otp_ctrl_dai.u_part_sel_idx

	Total	Covered	Percent
Conditions	118	106	89.83
Logical	118	106	89.83
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Excluded		vcs_gen_start:level=0,offset=0:vcs_gen_end:VC_COV_UNR
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T4

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Unreachable

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[3].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[3].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[4].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[4].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T4,T5

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T7,T8,T9

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Unreachable

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[7].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[7].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Unreachable
1	0	Unreachable

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[3].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[4].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[7].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[3].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[4].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[7].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[7].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[7].Pa] & gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Unreachable

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_otp_ctrl_dai.u_part_sel_idx

	Line No.	Total	Covered	Percent
Branches		54	48	88.89
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	1	0	0.00
TERNARY	110	1	0	0.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00
TERNARY	109	1	0	0.00
TERNARY	110	1	0	0.00
TERNARY	109	1	0	0.00
TERNARY	110	1	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

---

Assert Coverage for Instance : tb.dut.u_otp_ctrl_dai.u_part_sel_idx

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	7	53.85
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	7	53.85

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	462772914	461830240	0	0
CheckNGreaterZero_A	1155	1155	0	0
GntImpliesReady_A	462772914	0	0	0
GntImpliesValid_A	462772914	0	0	0
GrantKnown_A	462772914	461830240	0	0
IdxKnown_A	462772914	461830240	0	0
IndexIsCorrect_A	462772914	0	0	0
NoReadyValidNoGrant_A	462772914	0	0	0
Priority_A	462772914	461830240	0	0
ReadyAndValidImplyGrant_A	462772914	0	0	0
ReqAndReadyImplyGrant_A	462772914	0	0	0
ReqImpliesValid_A	462772914	461830240	0	0
ValidKnown_A	462772914	461830240	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	461830240	0	0
T1	13731	13469	0	0
T2	15356	15083	0	0
T3	18373	18108	0	0
T4	74889	73283	0	0
T5	678672	668007	0	0
T6	165586	164402	0	0
T7	117076	116813	0	0
T10	15102	14859	0	0
T11	9871	9672	0	0
T12	120257	119919	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1155	1155	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	461830240	0	0
T1	13731	13469	0	0
T2	15356	15083	0	0
T3	18373	18108	0	0
T4	74889	73283	0	0
T5	678672	668007	0	0
T6	165586	164402	0	0
T7	117076	116813	0	0
T10	15102	14859	0	0
T11	9871	9672	0	0
T12	120257	119919	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	461830240	0	0
T1	13731	13469	0	0
T2	15356	15083	0	0
T3	18373	18108	0	0
T4	74889	73283	0	0
T5	678672	668007	0	0
T6	165586	164402	0	0
T7	117076	116813	0	0
T10	15102	14859	0	0
T11	9871	9672	0	0
T12	120257	119919	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	461830240	0	0
T1	13731	13469	0	0
T2	15356	15083	0	0
T3	18373	18108	0	0
T4	74889	73283	0	0
T5	678672	668007	0	0
T6	165586	164402	0	0
T7	117076	116813	0	0
T10	15102	14859	0	0
T11	9871	9672	0	0
T12	120257	119919	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	461830240	0	0
T1	13731	13469	0	0
T2	15356	15083	0	0
T3	18373	18108	0	0
T4	74889	73283	0	0
T5	678672	668007	0	0
T6	165586	164402	0	0
T7	117076	116813	0	0
T10	15102	14859	0	0
T11	9871	9672	0	0
T12	120257	119919	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462772914	461830240	0	0
T1	13731	13469	0	0
T2	15356	15083	0	0
T3	18373	18108	0	0
T4	74889	73283	0	0
T5	678672	668007	0	0
T6	165586	164402	0	0
T7	117076	116813	0	0
T10	15102	14859	0	0
T11	9871	9672	0	0
T12	120257	119919	0	0