Unified Coverage Report :: Module :: prim_arbiter_tree

Module : prim_arbiter_tree

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.98	97.11	81.05			100.00	93.75

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_scrmbl_mtx	79.55	75.00	99.45			100.00	43.75
tb.dut.u_edn_arb	87.74	92.31	65.31			100.00	93.33
tb.dut.u_otp_arb	97.48	98.07	98.11			100.00	93.75
tb.dut.u_otp_ctrl_kdi.u_req_arb	98.34	100.00	99.62			100.00	93.75

Line Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=32,EnDataPort=0,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Line Coverage for Module self-instances :

SCORE	LINE
87.74	92.31

tb.dut.u_edn_arb

	Line No.	Total	Covered	Percent
TOTAL		26	24	92.31
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
112	2	2
118	2	2
122	0	2
126	2	2
128	2	2
148	1	1
150	1	1
151	1	1
155	1	1
156	1	1
160	1	1
161	1	1
163		unreachable
164	1	1
174	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Line Coverage for Module : prim_arbiter_tree ( parameter N=14,DW=83,EnDataPort=1,IdxW=4,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14,gen_normal_case.gen_tree[3].gen_level[0].Pa=7,gen_normal_case.gen_tree[3].gen_level[0].C0=15,gen_normal_case.gen_tree[3].gen_level[0].C1=16,gen_normal_case.gen_tree[3].gen_level[1].Pa=8,gen_normal_case.gen_tree[3].gen_level[1].C0=17,gen_normal_case.gen_tree[3].gen_level[1].C1=18,gen_normal_case.gen_tree[3].gen_level[2].Pa=9,gen_normal_case.gen_tree[3].gen_level[2].C0=19,gen_normal_case.gen_tree[3].gen_level[2].C1=20,gen_normal_case.gen_tree[3].gen_level[3].Pa=10,gen_normal_case.gen_tree[3].gen_level[3].C0=21,gen_normal_case.gen_tree[3].gen_level[3].C1=22,gen_normal_case.gen_tree[3].gen_level[4].Pa=11,gen_normal_case.gen_tree[3].gen_level[4].C0=23,gen_normal_case.gen_tree[3].gen_level[4].C1=24,gen_normal_case.gen_tree[3].gen_level[5].Pa=12,gen_normal_case.gen_tree[3].gen_level[5].C0=25,gen_normal_case.gen_tree[3].gen_level[5].C1=26,gen_normal_case.gen_tree[3].gen_level[6].Pa=13,gen_normal_case.gen_tree[3].gen_level[6].C0=27,gen_normal_case.gen_tree[3].gen_level[6].C1=28,gen_normal_case.gen_tree[3].gen_level[7].Pa=14,gen_normal_case.gen_tree[3].gen_level[7].C0=29,gen_normal_case.gen_tree[3].gen_level[7].C1=30,gen_normal_case.gen_tree[4].gen_level[0].Pa=15,gen_normal_case.gen_tree[4].gen_level[0].C0=31,gen_normal_case.gen_tree[4].gen_level[0].C1=32,gen_normal_case.gen_tree[4].gen_level[1].Pa=16,gen_normal_case.gen_tree[4].gen_level[1].C0=33,gen_normal_case.gen_tree[4].gen_level[1].C1=34,gen_normal_case.gen_tree[4].gen_level[2].Pa=17,gen_normal_case.gen_tree[4].gen_level[2].C0=35,gen_normal_case.gen_tree[4].gen_level[2].C1=36,gen_normal_case.gen_tree[4].gen_level[3].Pa=18,gen_normal_case.gen_tree[4].gen_level[3].C0=37,gen_normal_case.gen_tree[4].gen_level[3].C1=38,gen_normal_case.gen_tree[4].gen_level[4].Pa=19,gen_normal_case.gen_tree[4].gen_level[4].C0=39,gen_normal_case.gen_tree[4].gen_level[4].C1=40,gen_normal_case.gen_tree[4].gen_level[5].Pa=20,gen_normal_case.gen_tree[4].gen_level[5].C0=41,gen_normal_case.gen_tree[4].gen_level[5].C1=42,gen_normal_case.gen_tree[4].gen_level[6].Pa=21,gen_normal_case.gen_tree[4].gen_level[6].C0=43,gen_normal_case.gen_tree[4].gen_level[6].C1=44,gen_normal_case.gen_tree[4].gen_level[7].Pa=22,gen_normal_case.gen_tree[4].gen_level[7].C0=45,gen_normal_case.gen_tree[4].gen_level[7].C1=46,gen_normal_case.gen_tree[4].gen_level[8].Pa=23,gen_normal_case.gen_tree[4].gen_level[8].C0=47,gen_normal_case.gen_tree[4].gen_level[8].C1=48,gen_normal_case.gen_tree[4].gen_level[9].Pa=24,gen_normal_case.gen_tree[4].gen_level[9].C0=49,gen_normal_case.gen_tree[4].gen_level[9].C1=50,gen_normal_case.gen_tree[4].gen_level[10].Pa=25,gen_normal_case.gen_tree[4].gen_level[10].C0=51,gen_normal_case.gen_tree[4].gen_level[10].C1=52,gen_normal_case.gen_tree[4].gen_level[11].Pa=26,gen_normal_case.gen_tree[4].gen_level[11].C0=53,gen_normal_case.gen_tree[4].gen_level[11].C1=54,gen_normal_case.gen_tree[4].gen_level[12].Pa=27,gen_normal_case.gen_tree[4].gen_level[12].C0=55,gen_normal_case.gen_tree[4].gen_level[12].C1=56,gen_normal_case.gen_tree[4].gen_level[13].Pa=28,gen_normal_case.gen_tree[4].gen_level[13].C0=57,gen_normal_case.gen_tree[4].gen_level[13].C1=58,gen_normal_case.gen_tree[4].gen_level[14].Pa=29,gen_normal_case.gen_tree[4].gen_level[14].C0=59,gen_normal_case.gen_tree[4].gen_level[14].C1=60,gen_normal_case.gen_tree[4].gen_level[15].Pa=30,gen_normal_case.gen_tree[4].gen_level[15].C0=61,gen_normal_case.gen_tree[4].gen_level[15].C1=62 + N=14,DW=72,EnDataPort=1,IdxW=4,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14,gen_normal_case.gen_tree[3].gen_level[0].Pa=7,gen_normal_case.gen_tree[3].gen_level[0].C0=15,gen_normal_case.gen_tree[3].gen_level[0].C1=16,gen_normal_case.gen_tree[3].gen_level[1].Pa=8,gen_normal_case.gen_tree[3].gen_level[1].C0=17,gen_normal_case.gen_tree[3].gen_level[1].C1=18,gen_normal_case.gen_tree[3].gen_level[2].Pa=9,gen_normal_case.gen_tree[3].gen_level[2].C0=19,gen_normal_case.gen_tree[3].gen_level[2].C1=20,gen_normal_case.gen_tree[3].gen_level[3].Pa=10,gen_normal_case.gen_tree[3].gen_level[3].C0=21,gen_normal_case.gen_tree[3].gen_level[3].C1=22,gen_normal_case.gen_tree[3].gen_level[4].Pa=11,gen_normal_case.gen_tree[3].gen_level[4].C0=23,gen_normal_case.gen_tree[3].gen_level[4].C1=24,gen_normal_case.gen_tree[3].gen_level[5].Pa=12,gen_normal_case.gen_tree[3].gen_level[5].C0=25,gen_normal_case.gen_tree[3].gen_level[5].C1=26,gen_normal_case.gen_tree[3].gen_level[6].Pa=13,gen_normal_case.gen_tree[3].gen_level[6].C0=27,gen_normal_case.gen_tree[3].gen_level[6].C1=28,gen_normal_case.gen_tree[3].gen_level[7].Pa=14,gen_normal_case.gen_tree[3].gen_level[7].C0=29,gen_normal_case.gen_tree[3].gen_level[7].C1=30,gen_normal_case.gen_tree[4].gen_level[0].Pa=15,gen_normal_case.gen_tree[4].gen_level[0].C0=31,gen_normal_case.gen_tree[4].gen_level[0].C1=32,gen_normal_case.gen_tree[4].gen_level[1].Pa=16,gen_normal_case.gen_tree[4].gen_level[1].C0=33,gen_normal_case.gen_tree[4].gen_level[1].C1=34,gen_normal_case.gen_tree[4].gen_level[2].Pa=17,gen_normal_case.gen_tree[4].gen_level[2].C0=35,gen_normal_case.gen_tree[4].gen_level[2].C1=36,gen_normal_case.gen_tree[4].gen_level[3].Pa=18,gen_normal_case.gen_tree[4].gen_level[3].C0=37,gen_normal_case.gen_tree[4].gen_level[3].C1=38,gen_normal_case.gen_tree[4].gen_level[4].Pa=19,gen_normal_case.gen_tree[4].gen_level[4].C0=39,gen_normal_case.gen_tree[4].gen_level[4].C1=40,gen_normal_case.gen_tree[4].gen_level[5].Pa=20,gen_normal_case.gen_tree[4].gen_level[5].C0=41,gen_normal_case.gen_tree[4].gen_level[5].C1=42,gen_normal_case.gen_tree[4].gen_level[6].Pa=21,gen_normal_case.gen_tree[4].gen_level[6].C0=43,gen_normal_case.gen_tree[4].gen_level[6].C1=44,gen_normal_case.gen_tree[4].gen_level[7].Pa=22,gen_normal_case.gen_tree[4].gen_level[7].C0=45,gen_normal_case.gen_tree[4].gen_level[7].C1=46,gen_normal_case.gen_tree[4].gen_level[8].Pa=23,gen_normal_case.gen_tree[4].gen_level[8].C0=47,gen_normal_case.gen_tree[4].gen_level[8].C1=48,gen_normal_case.gen_tree[4].gen_level[9].Pa=24,gen_normal_case.gen_tree[4].gen_level[9].C0=49,gen_normal_case.gen_tree[4].gen_level[9].C1=50,gen_normal_case.gen_tree[4].gen_level[10].Pa=25,gen_normal_case.gen_tree[4].gen_level[10].C0=51,gen_normal_case.gen_tree[4].gen_level[10].C1=52,gen_normal_case.gen_tree[4].gen_level[11].Pa=26,gen_normal_case.gen_tree[4].gen_level[11].C0=53,gen_normal_case.gen_tree[4].gen_level[11].C1=54,gen_normal_case.gen_tree[4].gen_level[12].Pa=27,gen_normal_case.gen_tree[4].gen_level[12].C0=55,gen_normal_case.gen_tree[4].gen_level[12].C1=56,gen_normal_case.gen_tree[4].gen_level[13].Pa=28,gen_normal_case.gen_tree[4].gen_level[13].C0=57,gen_normal_case.gen_tree[4].gen_level[13].C1=58,gen_normal_case.gen_tree[4].gen_level[14].Pa=29,gen_normal_case.gen_tree[4].gen_level[14].C0=59,gen_normal_case.gen_tree[4].gen_level[14].C1=60,gen_normal_case.gen_tree[4].gen_level[15].Pa=30,gen_normal_case.gen_tree[4].gen_level[15].C0=61,gen_normal_case.gen_tree[4].gen_level[15].C1=62 )
Line Coverage for Module self-instances :

SCORE	LINE
97.48	98.07

tb.dut.u_otp_arb

SCORE	LINE
79.55	75.00

tb.dut.u_scrmbl_mtx

	Line No.	Total	Covered	Percent
TOTAL		207	205	99.03
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	0	0
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	0	0
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	0	0
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	1	1
112	14	14
118	14	14
122	14	14
126	14	14
128	14	14
138	2	2
148	14	14(1 unreachable)
150	14	14(1 unreachable)
151	14	14(1 unreachable)
155	14	15
156	14	15
160	14	14(1 unreachable)
161	15	15
163	11	11(4 unreachable)
164	15	15
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Line Coverage for Module : prim_arbiter_tree ( parameter N=7,DW=264,EnDataPort=1,IdxW=3,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14,gen_normal_case.gen_tree[3].gen_level[0].Pa=7,gen_normal_case.gen_tree[3].gen_level[0].C0=15,gen_normal_case.gen_tree[3].gen_level[0].C1=16,gen_normal_case.gen_tree[3].gen_level[1].Pa=8,gen_normal_case.gen_tree[3].gen_level[1].C0=17,gen_normal_case.gen_tree[3].gen_level[1].C1=18,gen_normal_case.gen_tree[3].gen_level[2].Pa=9,gen_normal_case.gen_tree[3].gen_level[2].C0=19,gen_normal_case.gen_tree[3].gen_level[2].C1=20,gen_normal_case.gen_tree[3].gen_level[3].Pa=10,gen_normal_case.gen_tree[3].gen_level[3].C0=21,gen_normal_case.gen_tree[3].gen_level[3].C1=22,gen_normal_case.gen_tree[3].gen_level[4].Pa=11,gen_normal_case.gen_tree[3].gen_level[4].C0=23,gen_normal_case.gen_tree[3].gen_level[4].C1=24,gen_normal_case.gen_tree[3].gen_level[5].Pa=12,gen_normal_case.gen_tree[3].gen_level[5].C0=25,gen_normal_case.gen_tree[3].gen_level[5].C1=26,gen_normal_case.gen_tree[3].gen_level[6].Pa=13,gen_normal_case.gen_tree[3].gen_level[6].C0=27,gen_normal_case.gen_tree[3].gen_level[6].C1=28,gen_normal_case.gen_tree[3].gen_level[7].Pa=14,gen_normal_case.gen_tree[3].gen_level[7].C0=29,gen_normal_case.gen_tree[3].gen_level[7].C1=30 )
Line Coverage for Module self-instances :

SCORE	LINE
98.34	100.00

tb.dut.u_otp_ctrl_kdi.u_req_arb

	Line No.	Total	Covered	Percent
TOTAL		103	103	100.00
CONT_ASSIGN	62	0	0
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	0	0
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	191	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62		unreachable
112	7	7
118	7	7
122	7	7
126	7	7
128	7	7
138	1	1
148	7	7
150	7	7
151	7	7
155	7	7
156	7	7
160	7	7
161	7	7
163	4	4(3 unreachable)
164	7	7
171	1	1
180	1	1
182	1	1
183	1	1
191	1	1
192	1	1
194	1	1

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=32,EnDataPort=0,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Cond Coverage for Module self-instances :

SCORE	COND
87.74	65.31

tb.dut.u_edn_arb

	Total	Covered	Percent
Conditions	51	32	62.75
Logical	51	32	62.75
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Not Covered

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T5,T6

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Covered	T4,T5,T6

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Not Covered

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T5,T6

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Unreachable

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=14,DW=83,EnDataPort=1,IdxW=4,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14,gen_normal_case.gen_tree[3].gen_level[0].Pa=7,gen_normal_case.gen_tree[3].gen_level[0].C0=15,gen_normal_case.gen_tree[3].gen_level[0].C1=16,gen_normal_case.gen_tree[3].gen_level[1].Pa=8,gen_normal_case.gen_tree[3].gen_level[1].C0=17,gen_normal_case.gen_tree[3].gen_level[1].C1=18,gen_normal_case.gen_tree[3].gen_level[2].Pa=9,gen_normal_case.gen_tree[3].gen_level[2].C0=19,gen_normal_case.gen_tree[3].gen_level[2].C1=20,gen_normal_case.gen_tree[3].gen_level[3].Pa=10,gen_normal_case.gen_tree[3].gen_level[3].C0=21,gen_normal_case.gen_tree[3].gen_level[3].C1=22,gen_normal_case.gen_tree[3].gen_level[4].Pa=11,gen_normal_case.gen_tree[3].gen_level[4].C0=23,gen_normal_case.gen_tree[3].gen_level[4].C1=24,gen_normal_case.gen_tree[3].gen_level[5].Pa=12,gen_normal_case.gen_tree[3].gen_level[5].C0=25,gen_normal_case.gen_tree[3].gen_level[5].C1=26,gen_normal_case.gen_tree[3].gen_level[6].Pa=13,gen_normal_case.gen_tree[3].gen_level[6].C0=27,gen_normal_case.gen_tree[3].gen_level[6].C1=28,gen_normal_case.gen_tree[3].gen_level[7].Pa=14,gen_normal_case.gen_tree[3].gen_level[7].C0=29,gen_normal_case.gen_tree[3].gen_level[7].C1=30,gen_normal_case.gen_tree[4].gen_level[0].Pa=15,gen_normal_case.gen_tree[4].gen_level[0].C0=31,gen_normal_case.gen_tree[4].gen_level[0].C1=32,gen_normal_case.gen_tree[4].gen_level[1].Pa=16,gen_normal_case.gen_tree[4].gen_level[1].C0=33,gen_normal_case.gen_tree[4].gen_level[1].C1=34,gen_normal_case.gen_tree[4].gen_level[2].Pa=17,gen_normal_case.gen_tree[4].gen_level[2].C0=35,gen_normal_case.gen_tree[4].gen_level[2].C1=36,gen_normal_case.gen_tree[4].gen_level[3].Pa=18,gen_normal_case.gen_tree[4].gen_level[3].C0=37,gen_normal_case.gen_tree[4].gen_level[3].C1=38,gen_normal_case.gen_tree[4].gen_level[4].Pa=19,gen_normal_case.gen_tree[4].gen_level[4].C0=39,gen_normal_case.gen_tree[4].gen_level[4].C1=40,gen_normal_case.gen_tree[4].gen_level[5].Pa=20,gen_normal_case.gen_tree[4].gen_level[5].C0=41,gen_normal_case.gen_tree[4].gen_level[5].C1=42,gen_normal_case.gen_tree[4].gen_level[6].Pa=21,gen_normal_case.gen_tree[4].gen_level[6].C0=43,gen_normal_case.gen_tree[4].gen_level[6].C1=44,gen_normal_case.gen_tree[4].gen_level[7].Pa=22,gen_normal_case.gen_tree[4].gen_level[7].C0=45,gen_normal_case.gen_tree[4].gen_level[7].C1=46,gen_normal_case.gen_tree[4].gen_level[8].Pa=23,gen_normal_case.gen_tree[4].gen_level[8].C0=47,gen_normal_case.gen_tree[4].gen_level[8].C1=48,gen_normal_case.gen_tree[4].gen_level[9].Pa=24,gen_normal_case.gen_tree[4].gen_level[9].C0=49,gen_normal_case.gen_tree[4].gen_level[9].C1=50,gen_normal_case.gen_tree[4].gen_level[10].Pa=25,gen_normal_case.gen_tree[4].gen_level[10].C0=51,gen_normal_case.gen_tree[4].gen_level[10].C1=52,gen_normal_case.gen_tree[4].gen_level[11].Pa=26,gen_normal_case.gen_tree[4].gen_level[11].C0=53,gen_normal_case.gen_tree[4].gen_level[11].C1=54,gen_normal_case.gen_tree[4].gen_level[12].Pa=27,gen_normal_case.gen_tree[4].gen_level[12].C0=55,gen_normal_case.gen_tree[4].gen_level[12].C1=56,gen_normal_case.gen_tree[4].gen_level[13].Pa=28,gen_normal_case.gen_tree[4].gen_level[13].C0=57,gen_normal_case.gen_tree[4].gen_level[13].C1=58,gen_normal_case.gen_tree[4].gen_level[14].Pa=29,gen_normal_case.gen_tree[4].gen_level[14].C0=59,gen_normal_case.gen_tree[4].gen_level[14].C1=60,gen_normal_case.gen_tree[4].gen_level[15].Pa=30,gen_normal_case.gen_tree[4].gen_level[15].C0=61,gen_normal_case.gen_tree[4].gen_level[15].C1=62 )
Cond Coverage for Module self-instances :

SCORE	COND
97.48	98.11

tb.dut.u_otp_arb

	Total	Covered	Percent
Conditions	559	519	92.84
Logical	559	519	92.84
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
118-155	90.59
155-164	98.71

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=14,DW=72,EnDataPort=1,IdxW=4,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14,gen_normal_case.gen_tree[3].gen_level[0].Pa=7,gen_normal_case.gen_tree[3].gen_level[0].C0=15,gen_normal_case.gen_tree[3].gen_level[0].C1=16,gen_normal_case.gen_tree[3].gen_level[1].Pa=8,gen_normal_case.gen_tree[3].gen_level[1].C0=17,gen_normal_case.gen_tree[3].gen_level[1].C1=18,gen_normal_case.gen_tree[3].gen_level[2].Pa=9,gen_normal_case.gen_tree[3].gen_level[2].C0=19,gen_normal_case.gen_tree[3].gen_level[2].C1=20,gen_normal_case.gen_tree[3].gen_level[3].Pa=10,gen_normal_case.gen_tree[3].gen_level[3].C0=21,gen_normal_case.gen_tree[3].gen_level[3].C1=22,gen_normal_case.gen_tree[3].gen_level[4].Pa=11,gen_normal_case.gen_tree[3].gen_level[4].C0=23,gen_normal_case.gen_tree[3].gen_level[4].C1=24,gen_normal_case.gen_tree[3].gen_level[5].Pa=12,gen_normal_case.gen_tree[3].gen_level[5].C0=25,gen_normal_case.gen_tree[3].gen_level[5].C1=26,gen_normal_case.gen_tree[3].gen_level[6].Pa=13,gen_normal_case.gen_tree[3].gen_level[6].C0=27,gen_normal_case.gen_tree[3].gen_level[6].C1=28,gen_normal_case.gen_tree[3].gen_level[7].Pa=14,gen_normal_case.gen_tree[3].gen_level[7].C0=29,gen_normal_case.gen_tree[3].gen_level[7].C1=30,gen_normal_case.gen_tree[4].gen_level[0].Pa=15,gen_normal_case.gen_tree[4].gen_level[0].C0=31,gen_normal_case.gen_tree[4].gen_level[0].C1=32,gen_normal_case.gen_tree[4].gen_level[1].Pa=16,gen_normal_case.gen_tree[4].gen_level[1].C0=33,gen_normal_case.gen_tree[4].gen_level[1].C1=34,gen_normal_case.gen_tree[4].gen_level[2].Pa=17,gen_normal_case.gen_tree[4].gen_level[2].C0=35,gen_normal_case.gen_tree[4].gen_level[2].C1=36,gen_normal_case.gen_tree[4].gen_level[3].Pa=18,gen_normal_case.gen_tree[4].gen_level[3].C0=37,gen_normal_case.gen_tree[4].gen_level[3].C1=38,gen_normal_case.gen_tree[4].gen_level[4].Pa=19,gen_normal_case.gen_tree[4].gen_level[4].C0=39,gen_normal_case.gen_tree[4].gen_level[4].C1=40,gen_normal_case.gen_tree[4].gen_level[5].Pa=20,gen_normal_case.gen_tree[4].gen_level[5].C0=41,gen_normal_case.gen_tree[4].gen_level[5].C1=42,gen_normal_case.gen_tree[4].gen_level[6].Pa=21,gen_normal_case.gen_tree[4].gen_level[6].C0=43,gen_normal_case.gen_tree[4].gen_level[6].C1=44,gen_normal_case.gen_tree[4].gen_level[7].Pa=22,gen_normal_case.gen_tree[4].gen_level[7].C0=45,gen_normal_case.gen_tree[4].gen_level[7].C1=46,gen_normal_case.gen_tree[4].gen_level[8].Pa=23,gen_normal_case.gen_tree[4].gen_level[8].C0=47,gen_normal_case.gen_tree[4].gen_level[8].C1=48,gen_normal_case.gen_tree[4].gen_level[9].Pa=24,gen_normal_case.gen_tree[4].gen_level[9].C0=49,gen_normal_case.gen_tree[4].gen_level[9].C1=50,gen_normal_case.gen_tree[4].gen_level[10].Pa=25,gen_normal_case.gen_tree[4].gen_level[10].C0=51,gen_normal_case.gen_tree[4].gen_level[10].C1=52,gen_normal_case.gen_tree[4].gen_level[11].Pa=26,gen_normal_case.gen_tree[4].gen_level[11].C0=53,gen_normal_case.gen_tree[4].gen_level[11].C1=54,gen_normal_case.gen_tree[4].gen_level[12].Pa=27,gen_normal_case.gen_tree[4].gen_level[12].C0=55,gen_normal_case.gen_tree[4].gen_level[12].C1=56,gen_normal_case.gen_tree[4].gen_level[13].Pa=28,gen_normal_case.gen_tree[4].gen_level[13].C0=57,gen_normal_case.gen_tree[4].gen_level[13].C1=58,gen_normal_case.gen_tree[4].gen_level[14].Pa=29,gen_normal_case.gen_tree[4].gen_level[14].C0=59,gen_normal_case.gen_tree[4].gen_level[14].C1=60,gen_normal_case.gen_tree[4].gen_level[15].Pa=30,gen_normal_case.gen_tree[4].gen_level[15].C0=61,gen_normal_case.gen_tree[4].gen_level[15].C1=62 )
Cond Coverage for Module self-instances :

SCORE	COND
79.55	99.45

tb.dut.u_scrmbl_mtx

	Total	Covered	Percent
Conditions	503	360	71.57
Logical	503	360	71.57
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
118-160	71.19
160-164	73.33

---

Cond Coverage for Module : prim_arbiter_tree ( parameter N=7,DW=264,EnDataPort=1,IdxW=3,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14,gen_normal_case.gen_tree[3].gen_level[0].Pa=7,gen_normal_case.gen_tree[3].gen_level[0].C0=15,gen_normal_case.gen_tree[3].gen_level[0].C1=16,gen_normal_case.gen_tree[3].gen_level[1].Pa=8,gen_normal_case.gen_tree[3].gen_level[1].C0=17,gen_normal_case.gen_tree[3].gen_level[1].C1=18,gen_normal_case.gen_tree[3].gen_level[2].Pa=9,gen_normal_case.gen_tree[3].gen_level[2].C0=19,gen_normal_case.gen_tree[3].gen_level[2].C1=20,gen_normal_case.gen_tree[3].gen_level[3].Pa=10,gen_normal_case.gen_tree[3].gen_level[3].C0=21,gen_normal_case.gen_tree[3].gen_level[3].C1=22,gen_normal_case.gen_tree[3].gen_level[4].Pa=11,gen_normal_case.gen_tree[3].gen_level[4].C0=23,gen_normal_case.gen_tree[3].gen_level[4].C1=24,gen_normal_case.gen_tree[3].gen_level[5].Pa=12,gen_normal_case.gen_tree[3].gen_level[5].C0=25,gen_normal_case.gen_tree[3].gen_level[5].C1=26,gen_normal_case.gen_tree[3].gen_level[6].Pa=13,gen_normal_case.gen_tree[3].gen_level[6].C0=27,gen_normal_case.gen_tree[3].gen_level[6].C1=28,gen_normal_case.gen_tree[3].gen_level[7].Pa=14,gen_normal_case.gen_tree[3].gen_level[7].C0=29,gen_normal_case.gen_tree[3].gen_level[7].C1=30 )
Cond Coverage for Module self-instances :

SCORE	COND
98.34	99.62

tb.dut.u_otp_ctrl_kdi.u_req_arb

	Total	Covered	Percent
Conditions	269	261	97.03
Logical	269	261	97.03
Non-Logical	0	0
Event	0	0

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       118
 EXPRESSION (req_i[2] & gen_normal_case.prio_mask_q[2])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       118
 EXPRESSION (req_i[3] & gen_normal_case.prio_mask_q[3])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T3,T4,T5

 LINE       118
 EXPRESSION (req_i[4] & gen_normal_case.prio_mask_q[4])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T4,T5

 LINE       118
 EXPRESSION (req_i[5] & gen_normal_case.prio_mask_q[5])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T4,T5

 LINE       118
 EXPRESSION (req_i[6] & gen_normal_case.prio_mask_q[6])
             ----1---   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T4,T5

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T9,T13
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T4,T5,T6

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T9,T13
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T5,T6

 LINE       126
 EXPRESSION (req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T9,T13
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T5,T6

 LINE       126
 EXPRESSION (req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T9,T13
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T4,T5,T6

 LINE       126
 EXPRESSION (req_i[4] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T9,T13,T31
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T5,T6

 LINE       126
 EXPRESSION (req_i[5] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T31,T64,T130
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T5,T6

 LINE       126
 EXPRESSION (req_i[6] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T13,T95
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T5,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T1,T4,T5
1	0	Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T4,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T4,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[2])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T4,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[3])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T4,T5

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T4,T5

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[4])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[5])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[6])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~ready_i))))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T5,T9,T13
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T5,T9,T13
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T266,T267,T268
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T67
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T5,T9,T13
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T67
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T5,T9,T13
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C1])

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T137,T269,T246
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C1])

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T67
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C1]))

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C1])

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Unreachable

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T4

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T4,T5

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T3,T4,T5

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T4,T5

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T4,T5,T6

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T3,T4,T5

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T3,T4,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T5,T6

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T3,T4,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T4,T5,T6

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T5,T6

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T3,T4,T5

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Covered	T4,T5,T6

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
1	0	Unreachable

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T13
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T4,T5

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T13
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T4,T5

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T13
1	0	Covered	T3,T4,T5
1	1	Covered	T4,T5,T6

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T9
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T3,T4,T5

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T4,T5,T6

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T4,T5

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T4

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Unreachable

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T4,T5

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T4

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T4

---

Branch Coverage for Module : prim_arbiter_tree ( parameter N=14,DW=83,EnDataPort=1,IdxW=4,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14,gen_normal_case.gen_tree[3].gen_level[0].Pa=7,gen_normal_case.gen_tree[3].gen_level[0].C0=15,gen_normal_case.gen_tree[3].gen_level[0].C1=16,gen_normal_case.gen_tree[3].gen_level[1].Pa=8,gen_normal_case.gen_tree[3].gen_level[1].C0=17,gen_normal_case.gen_tree[3].gen_level[1].C1=18,gen_normal_case.gen_tree[3].gen_level[2].Pa=9,gen_normal_case.gen_tree[3].gen_level[2].C0=19,gen_normal_case.gen_tree[3].gen_level[2].C1=20,gen_normal_case.gen_tree[3].gen_level[3].Pa=10,gen_normal_case.gen_tree[3].gen_level[3].C0=21,gen_normal_case.gen_tree[3].gen_level[3].C1=22,gen_normal_case.gen_tree[3].gen_level[4].Pa=11,gen_normal_case.gen_tree[3].gen_level[4].C0=23,gen_normal_case.gen_tree[3].gen_level[4].C1=24,gen_normal_case.gen_tree[3].gen_level[5].Pa=12,gen_normal_case.gen_tree[3].gen_level[5].C0=25,gen_normal_case.gen_tree[3].gen_level[5].C1=26,gen_normal_case.gen_tree[3].gen_level[6].Pa=13,gen_normal_case.gen_tree[3].gen_level[6].C0=27,gen_normal_case.gen_tree[3].gen_level[6].C1=28,gen_normal_case.gen_tree[3].gen_level[7].Pa=14,gen_normal_case.gen_tree[3].gen_level[7].C0=29,gen_normal_case.gen_tree[3].gen_level[7].C1=30,gen_normal_case.gen_tree[4].gen_level[0].Pa=15,gen_normal_case.gen_tree[4].gen_level[0].C0=31,gen_normal_case.gen_tree[4].gen_level[0].C1=32,gen_normal_case.gen_tree[4].gen_level[1].Pa=16,gen_normal_case.gen_tree[4].gen_level[1].C0=33,gen_normal_case.gen_tree[4].gen_level[1].C1=34,gen_normal_case.gen_tree[4].gen_level[2].Pa=17,gen_normal_case.gen_tree[4].gen_level[2].C0=35,gen_normal_case.gen_tree[4].gen_level[2].C1=36,gen_normal_case.gen_tree[4].gen_level[3].Pa=18,gen_normal_case.gen_tree[4].gen_level[3].C0=37,gen_normal_case.gen_tree[4].gen_level[3].C1=38,gen_normal_case.gen_tree[4].gen_level[4].Pa=19,gen_normal_case.gen_tree[4].gen_level[4].C0=39,gen_normal_case.gen_tree[4].gen_level[4].C1=40,gen_normal_case.gen_tree[4].gen_level[5].Pa=20,gen_normal_case.gen_tree[4].gen_level[5].C0=41,gen_normal_case.gen_tree[4].gen_level[5].C1=42,gen_normal_case.gen_tree[4].gen_level[6].Pa=21,gen_normal_case.gen_tree[4].gen_level[6].C0=43,gen_normal_case.gen_tree[4].gen_level[6].C1=44,gen_normal_case.gen_tree[4].gen_level[7].Pa=22,gen_normal_case.gen_tree[4].gen_level[7].C0=45,gen_normal_case.gen_tree[4].gen_level[7].C1=46,gen_normal_case.gen_tree[4].gen_level[8].Pa=23,gen_normal_case.gen_tree[4].gen_level[8].C0=47,gen_normal_case.gen_tree[4].gen_level[8].C1=48,gen_normal_case.gen_tree[4].gen_level[9].Pa=24,gen_normal_case.gen_tree[4].gen_level[9].C0=49,gen_normal_case.gen_tree[4].gen_level[9].C1=50,gen_normal_case.gen_tree[4].gen_level[10].Pa=25,gen_normal_case.gen_tree[4].gen_level[10].C0=51,gen_normal_case.gen_tree[4].gen_level[10].C1=52,gen_normal_case.gen_tree[4].gen_level[11].Pa=26,gen_normal_case.gen_tree[4].gen_level[11].C0=53,gen_normal_case.gen_tree[4].gen_level[11].C1=54,gen_normal_case.gen_tree[4].gen_level[12].Pa=27,gen_normal_case.gen_tree[4].gen_level[12].C0=55,gen_normal_case.gen_tree[4].gen_level[12].C1=56,gen_normal_case.gen_tree[4].gen_level[13].Pa=28,gen_normal_case.gen_tree[4].gen_level[13].C0=57,gen_normal_case.gen_tree[4].gen_level[13].C1=58,gen_normal_case.gen_tree[4].gen_level[14].Pa=29,gen_normal_case.gen_tree[4].gen_level[14].C0=59,gen_normal_case.gen_tree[4].gen_level[14].C1=60,gen_normal_case.gen_tree[4].gen_level[15].Pa=30,gen_normal_case.gen_tree[4].gen_level[15].C0=61,gen_normal_case.gen_tree[4].gen_level[15].C1=62 + N=14,DW=72,EnDataPort=1,IdxW=4,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14,gen_normal_case.gen_tree[3].gen_level[0].Pa=7,gen_normal_case.gen_tree[3].gen_level[0].C0=15,gen_normal_case.gen_tree[3].gen_level[0].C1=16,gen_normal_case.gen_tree[3].gen_level[1].Pa=8,gen_normal_case.gen_tree[3].gen_level[1].C0=17,gen_normal_case.gen_tree[3].gen_level[1].C1=18,gen_normal_case.gen_tree[3].gen_level[2].Pa=9,gen_normal_case.gen_tree[3].gen_level[2].C0=19,gen_normal_case.gen_tree[3].gen_level[2].C1=20,gen_normal_case.gen_tree[3].gen_level[3].Pa=10,gen_normal_case.gen_tree[3].gen_level[3].C0=21,gen_normal_case.gen_tree[3].gen_level[3].C1=22,gen_normal_case.gen_tree[3].gen_level[4].Pa=11,gen_normal_case.gen_tree[3].gen_level[4].C0=23,gen_normal_case.gen_tree[3].gen_level[4].C1=24,gen_normal_case.gen_tree[3].gen_level[5].Pa=12,gen_normal_case.gen_tree[3].gen_level[5].C0=25,gen_normal_case.gen_tree[3].gen_level[5].C1=26,gen_normal_case.gen_tree[3].gen_level[6].Pa=13,gen_normal_case.gen_tree[3].gen_level[6].C0=27,gen_normal_case.gen_tree[3].gen_level[6].C1=28,gen_normal_case.gen_tree[3].gen_level[7].Pa=14,gen_normal_case.gen_tree[3].gen_level[7].C0=29,gen_normal_case.gen_tree[3].gen_level[7].C1=30,gen_normal_case.gen_tree[4].gen_level[0].Pa=15,gen_normal_case.gen_tree[4].gen_level[0].C0=31,gen_normal_case.gen_tree[4].gen_level[0].C1=32,gen_normal_case.gen_tree[4].gen_level[1].Pa=16,gen_normal_case.gen_tree[4].gen_level[1].C0=33,gen_normal_case.gen_tree[4].gen_level[1].C1=34,gen_normal_case.gen_tree[4].gen_level[2].Pa=17,gen_normal_case.gen_tree[4].gen_level[2].C0=35,gen_normal_case.gen_tree[4].gen_level[2].C1=36,gen_normal_case.gen_tree[4].gen_level[3].Pa=18,gen_normal_case.gen_tree[4].gen_level[3].C0=37,gen_normal_case.gen_tree[4].gen_level[3].C1=38,gen_normal_case.gen_tree[4].gen_level[4].Pa=19,gen_normal_case.gen_tree[4].gen_level[4].C0=39,gen_normal_case.gen_tree[4].gen_level[4].C1=40,gen_normal_case.gen_tree[4].gen_level[5].Pa=20,gen_normal_case.gen_tree[4].gen_level[5].C0=41,gen_normal_case.gen_tree[4].gen_level[5].C1=42,gen_normal_case.gen_tree[4].gen_level[6].Pa=21,gen_normal_case.gen_tree[4].gen_level[6].C0=43,gen_normal_case.gen_tree[4].gen_level[6].C1=44,gen_normal_case.gen_tree[4].gen_level[7].Pa=22,gen_normal_case.gen_tree[4].gen_level[7].C0=45,gen_normal_case.gen_tree[4].gen_level[7].C1=46,gen_normal_case.gen_tree[4].gen_level[8].Pa=23,gen_normal_case.gen_tree[4].gen_level[8].C0=47,gen_normal_case.gen_tree[4].gen_level[8].C1=48,gen_normal_case.gen_tree[4].gen_level[9].Pa=24,gen_normal_case.gen_tree[4].gen_level[9].C0=49,gen_normal_case.gen_tree[4].gen_level[9].C1=50,gen_normal_case.gen_tree[4].gen_level[10].Pa=25,gen_normal_case.gen_tree[4].gen_level[10].C0=51,gen_normal_case.gen_tree[4].gen_level[10].C1=52,gen_normal_case.gen_tree[4].gen_level[11].Pa=26,gen_normal_case.gen_tree[4].gen_level[11].C0=53,gen_normal_case.gen_tree[4].gen_level[11].C1=54,gen_normal_case.gen_tree[4].gen_level[12].Pa=27,gen_normal_case.gen_tree[4].gen_level[12].C0=55,gen_normal_case.gen_tree[4].gen_level[12].C1=56,gen_normal_case.gen_tree[4].gen_level[13].Pa=28,gen_normal_case.gen_tree[4].gen_level[13].C0=57,gen_normal_case.gen_tree[4].gen_level[13].C1=58,gen_normal_case.gen_tree[4].gen_level[14].Pa=29,gen_normal_case.gen_tree[4].gen_level[14].C0=59,gen_normal_case.gen_tree[4].gen_level[14].C1=60,gen_normal_case.gen_tree[4].gen_level[15].Pa=30,gen_normal_case.gen_tree[4].gen_level[15].C0=61,gen_normal_case.gen_tree[4].gen_level[15].C1=62 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
97.48	100.00

tb.dut.u_otp_arb

SCORE	BRANCH
79.55	100.00

tb.dut.u_scrmbl_mtx

	Line No.	Total	Covered	Percent
Branches		88	88	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	1	1	100.00
TERNARY	156	1	1	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_tree ( parameter N=2,DW=32,EnDataPort=0,IdxW=1,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
87.74	100.00

tb.dut.u_edn_arb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_tree ( parameter N=7,DW=264,EnDataPort=1,IdxW=3,gen_normal_case.gen_tree[0].gen_level[0].Pa=0,gen_normal_case.gen_tree[0].gen_level[0].C0=1,gen_normal_case.gen_tree[0].gen_level[0].C1=2,gen_normal_case.gen_tree[1].gen_level[0].Pa=1,gen_normal_case.gen_tree[1].gen_level[0].C0=3,gen_normal_case.gen_tree[1].gen_level[0].C1=4,gen_normal_case.gen_tree[1].gen_level[1].Pa=2,gen_normal_case.gen_tree[1].gen_level[1].C0=5,gen_normal_case.gen_tree[1].gen_level[1].C1=6,gen_normal_case.gen_tree[2].gen_level[0].Pa=3,gen_normal_case.gen_tree[2].gen_level[0].C0=7,gen_normal_case.gen_tree[2].gen_level[0].C1=8,gen_normal_case.gen_tree[2].gen_level[1].Pa=4,gen_normal_case.gen_tree[2].gen_level[1].C0=9,gen_normal_case.gen_tree[2].gen_level[1].C1=10,gen_normal_case.gen_tree[2].gen_level[2].Pa=5,gen_normal_case.gen_tree[2].gen_level[2].C0=11,gen_normal_case.gen_tree[2].gen_level[2].C1=12,gen_normal_case.gen_tree[2].gen_level[3].Pa=6,gen_normal_case.gen_tree[2].gen_level[3].C0=13,gen_normal_case.gen_tree[2].gen_level[3].C1=14,gen_normal_case.gen_tree[3].gen_level[0].Pa=7,gen_normal_case.gen_tree[3].gen_level[0].C0=15,gen_normal_case.gen_tree[3].gen_level[0].C1=16,gen_normal_case.gen_tree[3].gen_level[1].Pa=8,gen_normal_case.gen_tree[3].gen_level[1].C0=17,gen_normal_case.gen_tree[3].gen_level[1].C1=18,gen_normal_case.gen_tree[3].gen_level[2].Pa=9,gen_normal_case.gen_tree[3].gen_level[2].C0=19,gen_normal_case.gen_tree[3].gen_level[2].C1=20,gen_normal_case.gen_tree[3].gen_level[3].Pa=10,gen_normal_case.gen_tree[3].gen_level[3].C0=21,gen_normal_case.gen_tree[3].gen_level[3].C1=22,gen_normal_case.gen_tree[3].gen_level[4].Pa=11,gen_normal_case.gen_tree[3].gen_level[4].C0=23,gen_normal_case.gen_tree[3].gen_level[4].C1=24,gen_normal_case.gen_tree[3].gen_level[5].Pa=12,gen_normal_case.gen_tree[3].gen_level[5].C0=25,gen_normal_case.gen_tree[3].gen_level[5].C1=26,gen_normal_case.gen_tree[3].gen_level[6].Pa=13,gen_normal_case.gen_tree[3].gen_level[6].C0=27,gen_normal_case.gen_tree[3].gen_level[6].C1=28,gen_normal_case.gen_tree[3].gen_level[7].Pa=14,gen_normal_case.gen_tree[3].gen_level[7].C0=29,gen_normal_case.gen_tree[3].gen_level[7].C1=30 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.34	100.00

tb.dut.u_otp_ctrl_kdi.u_req_arb

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	155	2	2	100.00
TERNARY	156	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
TERNARY	128	2	2	100.00
IF	191	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	155	(gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	156	(gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	128	((|req_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_tree

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1851091656	1847320960	0	0
CheckNGreaterZero_A	4620	4620	0	0
GntImpliesReady_A	1851091656	1981223	0	0
GntImpliesValid_A	1851091656	1981223	0	0
GrantKnown_A	1851091656	1847320960	0	0
IdxKnown_A	1851091656	1847320960	0	0
IndexIsCorrect_A	1851091656	1981223	0	0
LockArbDecision_A	1851091656	105663790	0	0
NoReadyValidNoGrant_A	1851091656	1248930973	0	0
ReadyAndValidImplyGrant_A	1851091656	1981223	0	0
ReqAndReadyImplyGrant_A	1851091656	1981223	0	0
ReqImpliesValid_A	1851091656	154777864	0	0
ReqStaysHighUntilGranted0_M	1851091656	105663790	0	0
RoundRobin_A	1851091656	0	0	4620
ValidKnown_A	1851091656	1847320960	0	0
gen_data_port_assertion.DataFlow_A	1388318742	1677701	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1851091656	1847320960	0	0
T1	54924	53876	0	0
T2	61424	60332	0	0
T3	73492	72432	0	0
T4	299556	293132	0	0
T5	2714688	2672028	0	0
T6	662344	657608	0	0
T7	468304	467252	0	0
T10	60408	59436	0	0
T11	39484	38688	0	0
T12	481028	479676	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4620	4620	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T10	4	4	0	0
T11	4	4	0	0
T12	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1851091656	1981223	0	0
T1	13731	127	0	0
T2	15356	248	0	0
T3	18373	169	0	0
T4	224667	4389	0	0
T5	2036016	24128	0	0
T6	496758	1491	0	0
T7	351228	302	0	0
T8	753552	941	0	0
T9	0	1979	0	0
T10	45306	226	0	0
T11	29613	123	0	0
T12	360771	217	0	0
T13	0	1516	0	0
T24	21422	0	0	0
T43	0	109	0	0
T100	68194	0	0	0
T103	0	156	0	0
T105	0	109	0	0
T149	0	427	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1851091656	1981223	0	0
T1	13731	127	0	0
T2	15356	248	0	0
T3	18373	169	0	0
T4	224667	4389	0	0
T5	2036016	24128	0	0
T6	496758	1491	0	0
T7	351228	302	0	0
T8	753552	941	0	0
T9	0	1979	0	0
T10	45306	226	0	0
T11	29613	123	0	0
T12	360771	217	0	0
T13	0	1516	0	0
T24	21422	0	0	0
T43	0	109	0	0
T100	68194	0	0	0
T103	0	156	0	0
T105	0	109	0	0
T149	0	427	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1851091656	1847320960	0	0
T1	54924	53876	0	0
T2	61424	60332	0	0
T3	73492	72432	0	0
T4	299556	293132	0	0
T5	2714688	2672028	0	0
T6	662344	657608	0	0
T7	468304	467252	0	0
T10	60408	59436	0	0
T11	39484	38688	0	0
T12	481028	479676	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1851091656	1847320960	0	0
T1	54924	53876	0	0
T2	61424	60332	0	0
T3	73492	72432	0	0
T4	299556	293132	0	0
T5	2714688	2672028	0	0
T6	662344	657608	0	0
T7	468304	467252	0	0
T10	60408	59436	0	0
T11	39484	38688	0	0
T12	481028	479676	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1851091656	1981223	0	0
T1	13731	127	0	0
T2	15356	248	0	0
T3	18373	169	0	0
T4	224667	4389	0	0
T5	2036016	24128	0	0
T6	496758	1491	0	0
T7	351228	302	0	0
T8	753552	941	0	0
T9	0	1979	0	0
T10	45306	226	0	0
T11	29613	123	0	0
T12	360771	217	0	0
T13	0	1516	0	0
T24	21422	0	0	0
T43	0	109	0	0
T100	68194	0	0	0
T103	0	156	0	0
T105	0	109	0	0
T149	0	427	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1851091656	105663790	0	0
T1	27462	8417	0	0
T2	30712	1872	0	0
T3	36746	12566	0	0
T4	224667	38790	0	0
T5	2036016	271696	0	0
T6	496758	122349	0	0
T7	351228	1872	0	0
T8	376776	502426	0	0
T9	0	142618	0	0
T10	45306	1185	0	0
T11	29613	644	0	0
T12	360771	112331	0	0
T13	0	13268	0	0
T24	10711	0	0	0
T43	0	7031	0	0
T100	34097	26082	0	0
T103	0	3980	0	0
T105	0	1282	0	0
T149	0	6081	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1851091656	1248930973	0	0
T1	54924	29346	0	0
T2	61424	41845	0	0
T3	73492	37759	0	0
T4	299556	155787	0	0
T5	2714688	1527084	0	0
T6	662344	315573	0	0
T7	468304	345968	0	0
T10	60408	41896	0	0
T11	39484	27251	0	0
T12	481028	242155	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1851091656	1981223	0	0
T1	13731	127	0	0
T2	15356	248	0	0
T3	18373	169	0	0
T4	224667	4389	0	0
T5	2036016	24128	0	0
T6	496758	1491	0	0
T7	351228	302	0	0
T8	753552	941	0	0
T9	0	1979	0	0
T10	45306	226	0	0
T11	29613	123	0	0
T12	360771	217	0	0
T13	0	1516	0	0
T24	21422	0	0	0
T43	0	109	0	0
T100	68194	0	0	0
T103	0	156	0	0
T105	0	109	0	0
T149	0	427	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1851091656	1981223	0	0
T1	13731	127	0	0
T2	15356	248	0	0
T3	18373	169	0	0
T4	224667	4389	0	0
T5	2036016	24128	0	0
T6	496758	1491	0	0
T7	351228	302	0	0
T8	753552	941	0	0
T9	0	1979	0	0
T10	45306	226	0	0
T11	29613	123	0	0
T12	360771	217	0	0
T13	0	1516	0	0
T24	21422	0	0	0
T43	0	109	0	0
T100	68194	0	0	0
T103	0	156	0	0
T105	0	109	0	0
T149	0	427	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1851091656	154777864	0	0
T1	41193	13178	0	0
T2	46068	7071	0	0
T3	55119	19370	0	0
T4	299556	97121	0	0
T5	2714688	696148	0	0
T6	662344	193561	0	0
T7	468304	8486	0	0
T8	376776	503370	0	0
T9	0	144601	0	0
T10	60408	6028	0	0
T11	39484	3447	0	0
T12	481028	121223	0	0
T13	0	14598	0	0
T24	10711	0	0	0
T43	0	7140	0	0
T100	34097	26083	0	0
T103	0	4116	0	0
T105	0	1377	0	0
T149	0	6453	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1851091656	105663790	0	0
T1	27462	8417	0	0
T2	30712	1872	0	0
T3	36746	12566	0	0
T4	224667	38790	0	0
T5	2036016	271696	0	0
T6	496758	122349	0	0
T7	351228	1872	0	0
T8	376776	502426	0	0
T9	0	142618	0	0
T10	45306	1185	0	0
T11	29613	644	0	0
T12	360771	112331	0	0
T13	0	13268	0	0
T24	10711	0	0	0
T43	0	7031	0	0
T100	34097	26082	0	0
T103	0	3980	0	0
T105	0	1282	0	0
T149	0	6081	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1851091656	0	0	4620

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1851091656	1847320960	0	0
T1	54924	53876	0	0
T2	61424	60332	0	0
T3	73492	72432	0	0
T4	299556	293132	0	0
T5	2714688	2672028	0	0
T6	662344	657608	0	0
T7	468304	467252	0	0
T10	60408	59436	0	0
T11	39484	38688	0	0
T12	481028	479676	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1388318742	1677701	0	0
T1	13731	127	0	0
T2	15356	248	0	0
T3	18373	169	0	0
T4	149778	3830	0	0
T5	1357344	20921	0	0
T6	331172	1218	0	0
T7	234152	302	0	0
T8	376776	161	0	0
T9	0	258	0	0
T10	30204	226	0	0
T11	19742	123	0	0
T12	240514	217	0	0
T13	0	186	0	0
T24	10711	0	0	0
T43	0	14	0	0
T100	34097	0	0	0
T103	0	21	0	0
T105	0	14	0	0
T149	0	56	0	0