Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_unbuf_access_lock_cg_wrap::unbuf_access_lock_cg

Group : otp_ctrl_env_pkg::otp_ctrl_unbuf_access_lock_cg_wrap::unbuf_access_lock_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

5 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
buf_err_code_cg_wrap[CreatorSwCfgIdx]	100.00	1	100	1	64	64
buf_err_code_cg_wrap[OwnerSwCfgIdx]	100.00	1	100	1	64	64
buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]	100.00	1	100	1	64	64
buf_err_code_cg_wrap[RotCreatorAuthStateIdx]	100.00	1	100	1	64	64
buf_err_code_cg_wrap[VendorTestIdx]	100.00	1	100	1	64	64

---

Group Instance : buf_err_code_cg_wrap[CreatorSwCfgIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OwnerSwCfgIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[RotCreatorAuthCodesignIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[RotCreatorAuthStateIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[RotCreatorAuthStateIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[RotCreatorAuthStateIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[RotCreatorAuthStateIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[VendorTestIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[VendorTestIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[VendorTestIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[VendorTestIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

28952

1

T1

14

T2

8

T3

2

write_op

6815

1

T1

1

T3

1

T5

4

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11834

1

T1

1

T3

1

T5

16

auto[1]

23933

1

T1

14

T2

8

T3

2

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26943

1

T1

15

T2

8

T3

3

auto[1]

8824

1

T35

19

T27

22

T13

10

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	5305	1			T5	12		T4	5		T8	2
auto[0]	auto[0]	write_op	2972	1			T1	1		T3	1		T5	4
auto[0]	auto[1]	read_op	2686	1			T35	11		T27	7		T7	23
auto[0]	auto[1]	write_op	871	1			T35	3		T27	2		T7	9
auto[1]	auto[0]	read_op	16504	1			T1	14		T2	8		T3	2
auto[1]	auto[0]	write_op	2162	1			T4	1		T6	3		T35	3
auto[1]	auto[1]	read_op	4457	1			T35	5		T27	10		T13	7
auto[1]	auto[1]	write_op	810	1			T27	3		T13	3		T7	3

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

29173

1

T1

9

T2

2

T3

1

write_op

6616

1

T1

2

T3

1

T5

1

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12029

1

T1

3

T3

1

T5

3

auto[1]

23760

1

T1

8

T2

2

T3

1

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30593

1

T1

11

T2

2

T3

2

auto[1]

5196

1

T35

4

T7

61

T28

35

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	6704	1			T1	1		T3	1		T5	2
auto[0]	auto[0]	write_op	3332	1			T1	2		T5	1		T4	9
auto[0]	auto[1]	read_op	1488	1			T7	24		T28	15		T73	74
auto[0]	auto[1]	write_op	505	1			T7	7		T28	5		T73	29
auto[1]	auto[0]	read_op	18271	1			T1	8		T2	2		T4	26
auto[1]	auto[0]	write_op	2286	1			T3	1		T6	1		T35	3
auto[1]	auto[1]	read_op	2710	1			T35	4		T7	25		T28	11
auto[1]	auto[1]	write_op	493	1			T7	5		T28	4		T73	27

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

28637

1

T1

19

T2

2

T5

6

write_op

6925

1

T1

1

T5

2

T4

12

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12050

1

T1

2

T5

8

T4

24

auto[1]

23512

1

T1

18

T2

2

T4

36

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26711

1

T1

20

T2

2

T5

8

auto[1]

8851

1

T35

16

T27

25

T13

7

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	5546	1			T1	1		T5	6		T4	13
auto[0]	auto[0]	write_op	3071	1			T1	1		T5	2		T4	11
auto[0]	auto[1]	read_op	2616	1			T35	6		T27	13		T7	25
auto[0]	auto[1]	write_op	817	1			T35	2		T27	3		T7	7
auto[1]	auto[0]	read_op	15956	1			T1	18		T2	2		T4	35
auto[1]	auto[0]	write_op	2138	1			T4	1		T6	1		T35	2
auto[1]	auto[1]	read_op	4519	1			T35	8		T27	7		T13	4
auto[1]	auto[1]	write_op	899	1			T27	2		T13	3		T7	4

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

27772

1

T1

16

T2

5

T5

4

write_op

4791

1

T1

1

T3

1

T5

2

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10600

1

T2

1

T3

1

T5

6

auto[1]

21963

1

T1

17

T2

4

T4

40

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28991

1

T1

17

T2

5

T3

1

auto[1]

3572

1

T27

22

T13

9

T7

21

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	6541	1			T2	1		T5	4		T4	7
auto[0]	auto[0]	write_op	2656	1			T3	1		T5	2		T4	6
auto[0]	auto[1]	read_op	1142	1			T27	4		T13	1		T7	8
auto[0]	auto[1]	write_op	261	1			T27	2		T13	1		T7	4
auto[1]	auto[0]	read_op	18134	1			T1	16		T2	4		T4	40
auto[1]	auto[0]	write_op	1660	1			T1	1		T35	2		T13	1
auto[1]	auto[1]	read_op	1955	1			T27	14		T13	5		T7	7
auto[1]	auto[1]	write_op	214	1			T27	2		T13	2		T7	2

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

27732

1

T1

12

T2

6

T3

3

write_op

6234

1

T1

1

T3

1

T5

4

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11847

1

T1

1

T5

18

T4

20

auto[1]

22119

1

T1

12

T2

6

T3

4

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25256

1

T1

13

T2

6

T3

4

auto[1]

8710

1

T35

18

T27

25

T13

6

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	5337	1			T5	14		T4	12		T8	8
auto[0]	auto[0]	write_op	2953	1			T1	1		T5	4		T4	8
auto[0]	auto[1]	read_op	2781	1			T35	4		T27	4		T7	23
auto[0]	auto[1]	write_op	776	1			T35	1		T27	1		T7	7
auto[1]	auto[0]	read_op	15146	1			T1	12		T2	6		T3	3
auto[1]	auto[0]	write_op	1820	1			T3	1		T4	1		T6	5
auto[1]	auto[1]	read_op	4468	1			T35	11		T27	17		T13	6
auto[1]	auto[1]	write_op	685	1			T35	2		T27	3		T7	13