SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[otp_ctrl_core_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[otp_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 21335524 | 1 | T1 | 5218 | T2 | 2688 | T3 | 1326 | ||||
auto[1] | 12305806 | 1 | T1 | 35 | T2 | 12 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 33641123 | 1 | T1 | 5253 | T2 | 2700 | T3 | 1328 | ||||
values[1] | 18 | 1 | T237 | 2 | T239 | 1 | T245 | 2 | ||||
values[2] | 3 | 1 | T326 | 1 | T327 | 1 | T328 | 1 | ||||
values[3] | 96 | 1 | T237 | 8 | T238 | 2 | T239 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 33641105 | 1 | T1 | 5253 | T2 | 2700 | T3 | 1328 | ||||
values[1] | 28 | 1 | T237 | 1 | T238 | 1 | T245 | 3 | ||||
values[2] | 7 | 1 | T237 | 1 | T245 | 1 | T329 | 1 | ||||
values[3] | 109 | 1 | T237 | 4 | T238 | 10 | T239 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 33641010 | 1 | T1 | 5253 | T2 | 2700 | T3 | 1328 | ||||
auto[TlIntgErrCmd] | 95 | 1 | T237 | 12 | T238 | 3 | T239 | 3 | ||||
auto[TlIntgErrData] | 113 | 1 | T237 | 4 | T238 | 8 | T239 | 2 | ||||
auto[TlIntgErrBoth] | 112 | 1 | T237 | 4 | T238 | 9 | T239 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 3325359 | 0 | T4 | 21820 | T6 | 40 | T13 | 20 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3325145 | 1 | T4 | 21820 | T6 | 40 | T13 | 20 | ||||
values[1] | 16 | 1 | T237 | 2 | T238 | 3 | T330 | 1 | ||||
values[2] | 4 | 1 | T331 | 1 | T332 | 2 | T327 | 1 | ||||
values[3] | 111 | 1 | T237 | 6 | T238 | 5 | T239 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3325147 | 1 | T4 | 21820 | T6 | 40 | T13 | 20 | ||||
values[1] | 26 | 1 | T237 | 1 | T238 | 2 | T239 | 1 | ||||
values[2] | 7 | 1 | T237 | 1 | T238 | 1 | T244 | 1 | ||||
values[3] | 100 | 1 | T237 | 7 | T238 | 8 | T239 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 3325039 | 1 | T4 | 21820 | T6 | 40 | T13 | 20 | ||||
auto[TlIntgErrCmd] | 108 | 1 | T237 | 8 | T238 | 4 | T239 | 3 | ||||
auto[TlIntgErrData] | 106 | 1 | T237 | 6 | T238 | 7 | T239 | 3 | ||||
auto[TlIntgErrBoth] | 106 | 1 | T237 | 6 | T238 | 9 | T239 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |