Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25224150

1

T1

2665

T2

1891

T3

1152

full_word

8417180

1

T1

2588

T2

809

T3

176

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33641010	1			T1	5253		T2	2700		T3	1328
auto[TlIntgErrCmd]	95	1			T237	12		T238	3		T239	3
auto[TlIntgErrData]	113	1			T237	4		T238	8		T239	2
auto[TlIntgErrBoth]	112	1			T237	4		T238	9		T239	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10153648

1

T1

4446

T2

2472

T3

1267

auto[1]

23487682

1

T1

807

T2

228

T3

61

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6427757	1			T1	2253		T2	1767		T3	1120
auto[TlIntgErrNone]	partial	auto[1]	18796100	1			T1	412		T2	124		T3	32
auto[TlIntgErrNone]	full_word	auto[0]	3725752	1			T1	2193		T2	705		T3	147
auto[TlIntgErrNone]	full_word	auto[1]	4691401	1			T1	395		T2	104		T3	29
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T237	3		T238	2		T239	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T237	6		T238	1		T239	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T237	2		T333	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T237	1		T329	1		T333	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T238	5		T239	1		T245	3
auto[TlIntgErrData]	partial	auto[1]	52	1			T237	4		T238	2		T239	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T238	1		T329	2		T334	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T331	1		T330	1		T334	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T237	1		T238	1		T239	4
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T237	3		T238	8		T239	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T332	1		T333	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T245	1		T244	1		T334	1