Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.94		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	489433760	7958148	0	0
check_regwen_rd_A	489433760	4160	0	0
check_timeout_rd_A	489433760	3624	0	0
check_trigger_regwen_rd_A	489433760	4439	0	0
consistency_check_period_rd_A	489433760	4523	0	0
creator_sw_cfg_read_lock_rd_A	489433760	3536	0	0
direct_access_address_rd_A	489433760	2691	0	0
direct_access_wdata_0_rd_A	489433760	1721	0	0
direct_access_wdata_1_rd_A	489433760	2003	0	0
integrity_check_period_rd_A	489433760	4306	0	0
intr_enable_rd_A	489433760	5397	0	0
owner_sw_cfg_read_lock_rd_A	489433760	3482	0	0
rot_creator_auth_codesign_read_lock_rd_A	489433760	3563	0	0
rot_creator_auth_state_read_lock_rd_A	489433760	3420	0	0
vendor_test_read_lock_rd_A	489433760	3290	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489433760	7958148	0	0
T4	263332	26631	0	0
T6	548632	98907	0	0
T7	104678	0	0	0
T8	10671	0	0	0
T9	7069	0	0	0
T10	16135	0	0	0
T11	15308	0	0	0
T12	0	100895	0	0
T13	47098	0	0	0
T14	0	23144	0	0
T15	0	98588	0	0
T16	0	121317	0	0
T17	0	48672	0	0
T27	96461	0	0	0
T35	34966	0	0	0
T38	0	153504	0	0
T223	0	190650	0	0
T246	0	40404	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489433760	4160	0	0
T12	697802	120	0	0
T14	0	17	0	0
T16	0	81	0	0
T17	0	76	0	0
T28	55709	0	0	0
T38	0	76	0	0
T43	10730	0	0	0
T64	15834	0	0	0
T72	14442	0	0	0
T89	3395	0	0	0
T90	71223	0	0	0
T97	39932	0	0	0
T98	5495	0	0	0
T159	11629	0	0	0
T165	0	77	0	0
T246	0	61	0	0
T253	0	74	0	0
T313	0	117	0	0
T314	0	144	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489433760	3624	0	0
T12	697802	112	0	0
T14	0	16	0	0
T16	0	80	0	0
T17	0	39	0	0
T28	55709	0	0	0
T38	0	106	0	0
T43	10730	0	0	0
T64	15834	0	0	0
T72	14442	0	0	0
T89	3395	0	0	0
T90	71223	0	0	0
T97	39932	0	0	0
T98	5495	0	0	0
T159	11629	0	0	0
T165	0	81	0	0
T246	0	80	0	0
T253	0	44	0	0
T313	0	176	0	0
T314	0	203	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489433760	4439	0	0
T12	697802	158	0	0
T14	0	16	0	0
T16	0	120	0	0
T17	0	44	0	0
T28	55709	0	0	0
T38	0	104	0	0
T43	10730	0	0	0
T64	15834	0	0	0
T72	14442	0	0	0
T89	3395	0	0	0
T90	71223	0	0	0
T97	39932	0	0	0
T98	5495	0	0	0
T159	11629	0	0	0
T165	0	100	0	0
T246	0	55	0	0
T253	0	68	0	0
T313	0	149	0	0
T314	0	165	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489433760	4523	0	0
T12	697802	96	0	0
T14	0	18	0	0
T16	0	79	0	0
T17	0	77	0	0
T28	55709	0	0	0
T38	0	97	0	0
T43	10730	0	0	0
T64	15834	0	0	0
T72	14442	0	0	0
T89	3395	0	0	0
T90	71223	0	0	0
T97	39932	0	0	0
T98	5495	0	0	0
T159	11629	0	0	0
T165	0	88	0	0
T246	0	58	0	0
T253	0	111	0	0
T313	0	110	0	0
T314	0	283	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489433760	3536	0	0
T12	697802	115	0	0
T14	0	11	0	0
T16	0	60	0	0
T17	0	97	0	0
T28	55709	0	0	0
T38	0	77	0	0
T43	10730	0	0	0
T64	15834	0	0	0
T72	14442	0	0	0
T89	3395	0	0	0
T90	71223	0	0	0
T97	39932	0	0	0
T98	5495	0	0	0
T159	11629	0	0	0
T165	0	101	0	0
T246	0	46	0	0
T253	0	76	0	0
T313	0	147	0	0
T314	0	208	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489433760	2691	0	0
T12	697802	118	0	0
T14	0	12	0	0
T16	0	92	0	0
T17	0	61	0	0
T28	55709	0	0	0
T38	0	91	0	0
T43	10730	0	0	0
T64	15834	0	0	0
T72	14442	0	0	0
T89	3395	0	0	0
T90	71223	0	0	0
T97	39932	0	0	0
T98	5495	0	0	0
T159	11629	0	0	0
T165	0	68	0	0
T246	0	44	0	0
T253	0	80	0	0
T313	0	146	0	0
T314	0	196	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489433760	1721	0	0
T12	697802	114	0	0
T16	0	94	0	0
T17	0	16	0	0
T28	55709	0	0	0
T38	0	59	0	0
T43	10730	0	0	0
T64	15834	0	0	0
T72	14442	0	0	0
T89	3395	0	0	0
T90	71223	0	0	0
T97	39932	0	0	0
T98	5495	0	0	0
T159	11629	0	0	0
T165	0	47	0	0
T246	0	39	0	0
T253	0	25	0	0
T256	0	21	0	0
T313	0	80	0	0
T314	0	108	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489433760	2003	0	0
T12	697802	106	0	0
T14	0	5	0	0
T16	0	50	0	0
T17	0	66	0	0
T28	55709	0	0	0
T38	0	114	0	0
T43	10730	0	0	0
T64	15834	0	0	0
T72	14442	0	0	0
T89	3395	0	0	0
T90	71223	0	0	0
T97	39932	0	0	0
T98	5495	0	0	0
T159	11629	0	0	0
T165	0	47	0	0
T246	0	67	0	0
T253	0	44	0	0
T313	0	135	0	0
T314	0	104	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489433760	4306	0	0
T12	697802	141	0	0
T14	0	12	0	0
T16	0	68	0	0
T17	0	74	0	0
T28	55709	0	0	0
T38	0	99	0	0
T43	10730	0	0	0
T64	15834	0	0	0
T72	14442	0	0	0
T89	3395	0	0	0
T90	71223	0	0	0
T97	39932	0	0	0
T98	5495	0	0	0
T159	11629	0	0	0
T165	0	93	0	0
T246	0	68	0	0
T253	0	85	0	0
T313	0	172	0	0
T314	0	163	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489433760	5397	0	0
T12	697802	135	0	0
T14	0	49	0	0
T16	0	150	0	0
T17	0	99	0	0
T28	55709	0	0	0
T38	0	80	0	0
T43	10730	0	0	0
T64	15834	0	0	0
T72	14442	0	0	0
T89	3395	0	0	0
T90	71223	0	0	0
T97	39932	0	0	0
T98	5495	0	0	0
T143	0	31	0	0
T159	11629	0	0	0
T165	0	77	0	0
T246	0	57	0	0
T253	0	94	0	0
T313	0	206	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489433760	3482	0	0
T12	697802	149	0	0
T14	0	25	0	0
T16	0	91	0	0
T17	0	80	0	0
T28	55709	0	0	0
T38	0	52	0	0
T43	10730	0	0	0
T64	15834	0	0	0
T72	14442	0	0	0
T89	3395	0	0	0
T90	71223	0	0	0
T97	39932	0	0	0
T98	5495	0	0	0
T159	11629	0	0	0
T165	0	101	0	0
T246	0	61	0	0
T253	0	136	0	0
T313	0	112	0	0
T314	0	171	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489433760	3563	0	0
T12	697802	97	0	0
T14	0	13	0	0
T16	0	97	0	0
T17	0	69	0	0
T28	55709	0	0	0
T38	0	120	0	0
T43	10730	0	0	0
T64	15834	0	0	0
T72	14442	0	0	0
T89	3395	0	0	0
T90	71223	0	0	0
T97	39932	0	0	0
T98	5495	0	0	0
T159	11629	0	0	0
T165	0	84	0	0
T246	0	61	0	0
T253	0	82	0	0
T313	0	137	0	0
T314	0	188	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489433760	3420	0	0
T12	697802	116	0	0
T14	0	22	0	0
T16	0	112	0	0
T17	0	82	0	0
T28	55709	0	0	0
T38	0	67	0	0
T43	10730	0	0	0
T64	15834	0	0	0
T72	14442	0	0	0
T89	3395	0	0	0
T90	71223	0	0	0
T97	39932	0	0	0
T98	5495	0	0	0
T159	11629	0	0	0
T165	0	72	0	0
T246	0	44	0	0
T253	0	110	0	0
T313	0	117	0	0
T314	0	160	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489433760	3290	0	0
T12	697802	125	0	0
T14	0	44	0	0
T16	0	107	0	0
T17	0	92	0	0
T28	55709	0	0	0
T38	0	80	0	0
T43	10730	0	0	0
T64	15834	0	0	0
T72	14442	0	0	0
T89	3395	0	0	0
T90	71223	0	0	0
T97	39932	0	0	0
T98	5495	0	0	0
T159	11629	0	0	0
T165	0	101	0	0
T246	0	29	0	0
T253	0	70	0	0
T313	0	102	0	0
T314	0	176	0	0