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Module Instance : tb.dut.u_edn_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.74 92.31 65.31 100.00 93.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.74 92.31 65.31 100.00 93.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.17 94.16 96.15 96.94 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instances:
tb.dut.u_edn_arb
Line Coverage for Instance : tb.dut.u_edn_arb
Line No.TotalCoveredPercent
TOTAL262492.31
CONT_ASSIGN6211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN122100.00
CONT_ASSIGN122100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16300
CONT_ASSIGN16411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
CONT_ASSIGN18311100.00
ALWAYS19133100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
112 2 2
118 2 2
122 0 2
126 2 2
128 2 2
148 1 1
150 1 1
151 1 1
155 1 1
156 1 1
160 1 1
161 1 1
163 unreachable
164 1 1
174 1 1
180 1 1
182 1 1
183 1 1
191 1 1
192 1 1
194 1 1


Cond Coverage for Instance : tb.dut.u_edn_arb
TotalCoveredPercent
Conditions493265.31
Logical493265.31
Non-Logical00
Event00

 LINE       118
 EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
             ----1---   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01Excluded vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR
10CoveredT1,T3,T4
11CoveredT1,T3,T4

 LINE       118
 EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
             ----1---   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T3,T4
10Not Covered
11Not Covered

 LINE       126
 EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTestsExclude Annotation
011Excluded vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR
101Not Covered
110CoveredT1,T3,T4
111CoveredT1,T3,T4

 LINE       126
 EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
             ----1---   ----------------------------------2----------------------------------   ---3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1--2-StatusTests
00CoveredT1,T3,T4
01CoveredT1,T3,T4
10Unreachable

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T4
11CoveredT1,T3,T4

 LINE       128
 EXPRESSION 
 Number  Term
      1  ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       128
 SUB-EXPRESSION 
 Number  Term
      1  gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | 
      2  (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1--2-StatusTests
00Not Covered
01Not Covered
10CoveredT1,T3,T4

 LINE       128
 SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
                 ----------------------------------1----------------------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T3,T4
10Not Covered
11Not Covered

 LINE       148
 EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) | 
      2  (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1--2-StatusTests
00CoveredT1,T3,T4
01Not Covered
10CoveredT1,T2,T3

 LINE       148
 SUB-EXPRESSION 
 Number  Term
      1  ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & 
      2  gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       150
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T3,T4

 LINE       151
 EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   -----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10Not Covered

 LINE       155
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T3,T4
1CoveredT1,T2,T3

 LINE       160
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT1,T3,T4

 LINE       161
 EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Unreachable
10CoveredT1,T3,T4
11CoveredT1,T2,T3

 LINE       164
 EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
             -----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T4
10Unreachable

Branch Coverage for Instance : tb.dut.u_edn_arb
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 155 2 2 100.00
TERNARY 156 2 2 100.00
TERNARY 128 2 2 100.00
TERNARY 128 2 2 100.00
IF 191 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T4


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 128 ((|req_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 14 93.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 14 93.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 486419960 485523430 0 0
CheckNGreaterZero_A 1150 1150 0 0
GntImpliesReady_A 486419960 282273 0 0
GntImpliesValid_A 486419960 282273 0 0
GrantKnown_A 486419960 485523430 0 0
IdxKnown_A 486419960 485523430 0 0
IndexIsCorrect_A 486419960 282273 0 0
LockArbDecision_A 486419960 15962410 0 0
NoReadyValidNoGrant_A 486419960 469255181 0 0
ReadyAndValidImplyGrant_A 486419960 282273 0 0
ReqAndReadyImplyGrant_A 486419960 282273 0 0
ReqImpliesValid_A 486419960 16268249 0 0
ReqStaysHighUntilGranted0_M 486419960 15962410 0 0
RoundRobin_A 486419960 0 0 1150
ValidKnown_A 486419960 485523430 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 486419960 485523430 0 0
T1 66844 66569 0 0
T2 13542 13268 0 0
T3 15893 15536 0 0
T4 263332 263308 0 0
T5 14662 14407 0 0
T6 548632 548605 0 0
T8 10671 10511 0 0
T9 7069 6986 0 0
T10 16135 15828 0 0
T11 15308 15021 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1150 1150 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 486419960 282273 0 0
T1 66844 46 0 0
T2 13542 0 0 0
T3 15893 45 0 0
T4 263332 363 0 0
T5 14662 0 0 0
T6 548632 46 0 0
T7 0 1745 0 0
T8 10671 0 0 0
T9 7069 0 0 0
T10 16135 0 0 0
T11 15308 0 0 0
T12 0 651 0 0
T13 0 138 0 0
T27 0 511 0 0
T35 0 185 0 0
T88 0 48 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 486419960 282273 0 0
T1 66844 46 0 0
T2 13542 0 0 0
T3 15893 45 0 0
T4 263332 363 0 0
T5 14662 0 0 0
T6 548632 46 0 0
T7 0 1745 0 0
T8 10671 0 0 0
T9 7069 0 0 0
T10 16135 0 0 0
T11 15308 0 0 0
T12 0 651 0 0
T13 0 138 0 0
T27 0 511 0 0
T35 0 185 0 0
T88 0 48 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 486419960 485523430 0 0
T1 66844 66569 0 0
T2 13542 13268 0 0
T3 15893 15536 0 0
T4 263332 263308 0 0
T5 14662 14407 0 0
T6 548632 548605 0 0
T8 10671 10511 0 0
T9 7069 6986 0 0
T10 16135 15828 0 0
T11 15308 15021 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 486419960 485523430 0 0
T1 66844 66569 0 0
T2 13542 13268 0 0
T3 15893 15536 0 0
T4 263332 263308 0 0
T5 14662 14407 0 0
T6 548632 548605 0 0
T8 10671 10511 0 0
T9 7069 6986 0 0
T10 16135 15828 0 0
T11 15308 15021 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 486419960 282273 0 0
T1 66844 46 0 0
T2 13542 0 0 0
T3 15893 45 0 0
T4 263332 363 0 0
T5 14662 0 0 0
T6 548632 46 0 0
T7 0 1745 0 0
T8 10671 0 0 0
T9 7069 0 0 0
T10 16135 0 0 0
T11 15308 0 0 0
T12 0 651 0 0
T13 0 138 0 0
T27 0 511 0 0
T35 0 185 0 0
T88 0 48 0 0

LockArbDecision_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 486419960 15962410 0 0
T1 66844 1983 0 0
T2 13542 0 0 0
T3 15893 1329 0 0
T4 263332 23823 0 0
T5 14662 0 0 0
T6 548632 840 0 0
T7 0 168141 0 0
T8 10671 0 0 0
T9 7069 0 0 0
T10 16135 0 0 0
T11 15308 0 0 0
T12 0 5860 0 0
T13 0 2367 0 0
T27 0 21623 0 0
T35 0 2901 0 0
T88 0 646 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 486419960 469255181 0 0
T1 66844 64540 0 0
T2 13542 13268 0 0
T3 15893 14162 0 0
T4 263332 260889 0 0
T5 14662 14407 0 0
T6 548632 548517 0 0
T8 10671 10511 0 0
T9 7069 6986 0 0
T10 16135 15828 0 0
T11 15308 15021 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 486419960 282273 0 0
T1 66844 46 0 0
T2 13542 0 0 0
T3 15893 45 0 0
T4 263332 363 0 0
T5 14662 0 0 0
T6 548632 46 0 0
T7 0 1745 0 0
T8 10671 0 0 0
T9 7069 0 0 0
T10 16135 0 0 0
T11 15308 0 0 0
T12 0 651 0 0
T13 0 138 0 0
T27 0 511 0 0
T35 0 185 0 0
T88 0 48 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 486419960 282273 0 0
T1 66844 46 0 0
T2 13542 0 0 0
T3 15893 45 0 0
T4 263332 363 0 0
T5 14662 0 0 0
T6 548632 46 0 0
T7 0 1745 0 0
T8 10671 0 0 0
T9 7069 0 0 0
T10 16135 0 0 0
T11 15308 0 0 0
T12 0 651 0 0
T13 0 138 0 0
T27 0 511 0 0
T35 0 185 0 0
T88 0 48 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 486419960 16268249 0 0
T1 66844 2029 0 0
T2 13542 0 0 0
T3 15893 1374 0 0
T4 263332 24186 0 0
T5 14662 0 0 0
T6 548632 886 0 0
T7 0 169888 0 0
T8 10671 0 0 0
T9 7069 0 0 0
T10 16135 0 0 0
T11 15308 0 0 0
T12 0 6511 0 0
T13 0 2505 0 0
T27 0 22134 0 0
T35 0 3086 0 0
T88 0 694 0 0

ReqStaysHighUntilGranted0_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 486419960 15962410 0 0
T1 66844 1983 0 0
T2 13542 0 0 0
T3 15893 1329 0 0
T4 263332 23823 0 0
T5 14662 0 0 0
T6 548632 840 0 0
T7 0 168141 0 0
T8 10671 0 0 0
T9 7069 0 0 0
T10 16135 0 0 0
T11 15308 0 0 0
T12 0 5860 0 0
T13 0 2367 0 0
T27 0 21623 0 0
T35 0 2901 0 0
T88 0 646 0 0

RoundRobin_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 486419960 0 0 1150

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 486419960 485523430 0 0
T1 66844 66569 0 0
T2 13542 13268 0 0
T3 15893 15536 0 0
T4 263332 263308 0 0
T5 14662 14407 0 0
T6 548632 548605 0 0
T8 10671 10511 0 0
T9 7069 6986 0 0
T10 16135 15828 0 0
T11 15308 15021 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%