Line Coverage for Module :
otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=1720,StateWidth=12 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 160 | 127 | 79.38 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
ALWAYS | 206 | 140 | 107 | 76.43 |
CONT_ASSIGN | 636 | 1 | 1 | 100.00 |
CONT_ASSIGN | 641 | 1 | 1 | 100.00 |
CONT_ASSIGN | 642 | 1 | 1 | 100.00 |
CONT_ASSIGN | 646 | 1 | 1 | 100.00 |
CONT_ASSIGN | 652 | 1 | 1 | 100.00 |
CONT_ASSIGN | 675 | 1 | 1 | 100.00 |
CONT_ASSIGN | 678 | 1 | 1 | 100.00 |
CONT_ASSIGN | 680 | 1 | 1 | 100.00 |
CONT_ASSIGN | 709 | 1 | 1 | 100.00 |
CONT_ASSIGN | 743 | 1 | 1 | 100.00 |
ALWAYS | 750 | 3 | 3 | 100.00 |
ALWAYS | 753 | 5 | 5 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
182 |
1 |
1 |
193 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
212 |
1 |
1 |
215 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
224 |
1 |
1 |
225 |
1 |
1 |
226 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
237 |
1 |
1 |
238 |
1 |
1 |
240 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
254 |
1 |
1 |
255 |
1 |
1 |
256 |
1 |
1 |
|
|
|
MISSING_ELSE |
265 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
271 |
1 |
1 |
272 |
1 |
1 |
275 |
1 |
1 |
276 |
|
unreachable |
278 |
1 |
1 |
279 |
1 |
1 |
282 |
1 |
1 |
283 |
1 |
1 |
|
|
|
MISSING_ELSE |
286 |
1 |
1 |
287 |
1 |
1 |
|
|
|
MISSING_ELSE |
298 |
0 |
1 |
299 |
0 |
1 |
300 |
0 |
1 |
301 |
0 |
1 |
302 |
0 |
1 |
303 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
311 |
0 |
1 |
312 |
0 |
1 |
313 |
0 |
1 |
314 |
0 |
1 |
315 |
0 |
1 |
316 |
0 |
1 |
317 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
324 |
1 |
1 |
325 |
1 |
1 |
326 |
1 |
1 |
331 |
|
unreachable |
333 |
1 |
1 |
334 |
1 |
1 |
335 |
1 |
1 |
|
|
|
MISSING_ELSE |
343 |
1 |
1 |
348 |
1 |
1 |
349 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
351 |
1 |
1 |
352 |
1 |
1 |
|
|
|
MISSING_ELSE |
362 |
1 |
1 |
363 |
1 |
1 |
366 |
1 |
1 |
368 |
1 |
1 |
369 |
1 |
1 |
370 |
1 |
1 |
373 |
1 |
1 |
374 |
1 |
1 |
376 |
1 |
1 |
381 |
|
unreachable |
385 |
|
unreachable |
386 |
|
unreachable |
387 |
|
unreachable |
390 |
|
unreachable |
391 |
|
unreachable |
394 |
|
unreachable |
395 |
|
unreachable |
397 |
|
unreachable |
401 |
1 |
1 |
402 |
1 |
1 |
|
|
|
MISSING_ELSE |
405 |
1 |
1 |
406 |
1 |
1 |
408 |
1 |
1 |
|
|
|
MISSING_ELSE |
417 |
1 |
1 |
418 |
1 |
1 |
419 |
1 |
1 |
420 |
1 |
1 |
423 |
1 |
1 |
424 |
1 |
1 |
425 |
|
unreachable |
426 |
|
unreachable |
427 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
432 |
1 |
1 |
433 |
1 |
1 |
434 |
1 |
1 |
|
|
|
MISSING_ELSE |
443 |
|
unreachable |
444 |
|
unreachable |
445 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
455 |
0 |
1 |
456 |
0 |
1 |
457 |
0 |
1 |
458 |
0 |
1 |
459 |
0 |
1 |
460 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
467 |
0 |
1 |
468 |
0 |
1 |
469 |
0 |
1 |
470 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
480 |
1 |
1 |
481 |
1 |
1 |
482 |
1 |
1 |
483 |
1 |
1 |
485 |
1 |
1 |
489 |
1 |
1 |
490 |
1 |
1 |
491 |
1 |
1 |
493 |
0 |
1 |
494 |
0 |
1 |
498 |
1 |
1 |
499 |
1 |
1 |
|
|
|
MISSING_ELSE |
503 |
1 |
1 |
504 |
|
unreachable |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
516 |
0 |
1 |
517 |
0 |
1 |
518 |
0 |
1 |
519 |
0 |
1 |
520 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
528 |
1 |
1 |
529 |
1 |
1 |
530 |
1 |
1 |
531 |
1 |
1 |
532 |
1 |
1 |
|
|
|
MISSING_ELSE |
542 |
1 |
1 |
543 |
1 |
1 |
544 |
1 |
1 |
547 |
1 |
1 |
548 |
1 |
1 |
551 |
1 |
1 |
552 |
1 |
1 |
556 |
1 |
1 |
560 |
1 |
1 |
561 |
1 |
1 |
563 |
1 |
1 |
|
|
|
MISSING_ELSE |
572 |
1 |
1 |
573 |
1 |
1 |
574 |
1 |
1 |
|
|
|
MISSING_ELSE |
578 |
1 |
1 |
579 |
1 |
1 |
595 |
1 |
1 |
596 |
0 |
1 |
597 |
0 |
1 |
598 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
|
|
|
MISSING_ELSE |
602 |
1 |
1 |
603 |
1 |
1 |
604 |
1 |
1 |
605 |
1 |
1 |
606 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
636 |
1 |
1 |
641 |
1 |
1 |
642 |
1 |
1 |
646 |
1 |
1 |
652 |
1 |
1 |
675 |
1 |
1 |
678 |
1 |
1 |
680 |
1 |
1 |
709 |
1 |
1 |
743 |
1 |
1 |
750 |
3 |
3 |
753 |
1 |
1 |
754 |
1 |
1 |
756 |
1 |
1 |
758 |
1 |
1 |
759 |
1 |
1 |
Line Coverage for Module :
otp_ctrl_part_buf ( parameter Info=-1,CntWidth=1,DigestOffset=1736,StateWidth=12 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 160 | 126 | 78.75 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
ALWAYS | 206 | 140 | 106 | 75.71 |
CONT_ASSIGN | 636 | 1 | 1 | 100.00 |
CONT_ASSIGN | 641 | 1 | 1 | 100.00 |
CONT_ASSIGN | 642 | 1 | 1 | 100.00 |
CONT_ASSIGN | 646 | 1 | 1 | 100.00 |
CONT_ASSIGN | 652 | 1 | 1 | 100.00 |
CONT_ASSIGN | 675 | 1 | 1 | 100.00 |
CONT_ASSIGN | 678 | 1 | 1 | 100.00 |
CONT_ASSIGN | 680 | 1 | 1 | 100.00 |
CONT_ASSIGN | 709 | 1 | 1 | 100.00 |
CONT_ASSIGN | 743 | 1 | 1 | 100.00 |
ALWAYS | 750 | 3 | 3 | 100.00 |
ALWAYS | 753 | 5 | 5 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
182 |
1 |
1 |
193 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
212 |
1 |
1 |
215 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
224 |
1 |
1 |
225 |
1 |
1 |
226 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
237 |
1 |
1 |
238 |
1 |
1 |
240 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
254 |
1 |
1 |
255 |
1 |
1 |
256 |
1 |
1 |
|
|
|
MISSING_ELSE |
265 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
271 |
1 |
1 |
272 |
1 |
1 |
275 |
1 |
1 |
276 |
|
unreachable |
278 |
1 |
1 |
279 |
1 |
1 |
282 |
1 |
1 |
283 |
1 |
1 |
|
|
|
MISSING_ELSE |
286 |
1 |
1 |
287 |
1 |
1 |
|
|
|
MISSING_ELSE |
298 |
0 |
1 |
299 |
0 |
1 |
300 |
0 |
1 |
301 |
0 |
1 |
302 |
0 |
1 |
303 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
311 |
0 |
1 |
312 |
0 |
1 |
313 |
0 |
1 |
314 |
0 |
1 |
315 |
0 |
1 |
316 |
0 |
1 |
317 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
324 |
1 |
1 |
325 |
1 |
1 |
326 |
1 |
1 |
331 |
|
unreachable |
333 |
1 |
1 |
334 |
1 |
1 |
335 |
1 |
1 |
|
|
|
MISSING_ELSE |
343 |
1 |
1 |
348 |
1 |
1 |
349 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
351 |
1 |
1 |
352 |
1 |
1 |
|
|
|
MISSING_ELSE |
362 |
1 |
1 |
363 |
1 |
1 |
366 |
1 |
1 |
368 |
1 |
1 |
369 |
1 |
1 |
370 |
1 |
1 |
373 |
0 |
1 |
374 |
0 |
1 |
376 |
0 |
1 |
381 |
|
unreachable |
385 |
|
unreachable |
386 |
|
unreachable |
387 |
|
unreachable |
390 |
|
unreachable |
391 |
|
unreachable |
394 |
|
unreachable |
395 |
|
unreachable |
397 |
|
unreachable |
401 |
1 |
1 |
402 |
1 |
1 |
|
|
|
MISSING_ELSE |
405 |
1 |
1 |
406 |
1 |
1 |
408 |
1 |
1 |
|
|
|
MISSING_ELSE |
417 |
1 |
1 |
418 |
1 |
1 |
419 |
1 |
1 |
420 |
1 |
1 |
423 |
1 |
1 |
424 |
1 |
1 |
425 |
|
unreachable |
426 |
|
unreachable |
427 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
432 |
1 |
1 |
433 |
1 |
1 |
434 |
1 |
1 |
|
|
|
MISSING_ELSE |
443 |
|
unreachable |
444 |
|
unreachable |
445 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
455 |
0 |
1 |
456 |
0 |
1 |
457 |
0 |
1 |
458 |
0 |
1 |
459 |
0 |
1 |
460 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
467 |
0 |
1 |
468 |
0 |
1 |
469 |
0 |
1 |
470 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
480 |
1 |
1 |
481 |
1 |
1 |
482 |
1 |
1 |
483 |
1 |
1 |
485 |
1 |
1 |
489 |
1 |
1 |
490 |
0 |
1 |
491 |
0 |
1 |
493 |
1 |
1 |
494 |
1 |
1 |
498 |
0 |
1 |
499 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
503 |
0 |
1 |
504 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
|
|
|
==> MISSING_ELSE |
516 |
1 |
1 |
517 |
1 |
1 |
518 |
1 |
1 |
519 |
1 |
1 |
520 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
528 |
1 |
1 |
529 |
1 |
1 |
530 |
1 |
1 |
531 |
1 |
1 |
532 |
1 |
1 |
|
|
|
MISSING_ELSE |
542 |
1 |
1 |
543 |
1 |
1 |
544 |
1 |
1 |
547 |
1 |
1 |
548 |
1 |
1 |
551 |
1 |
1 |
552 |
1 |
1 |
556 |
1 |
1 |
560 |
1 |
1 |
561 |
1 |
1 |
563 |
1 |
1 |
|
|
|
MISSING_ELSE |
572 |
1 |
1 |
573 |
1 |
1 |
574 |
1 |
1 |
|
|
|
MISSING_ELSE |
578 |
1 |
1 |
579 |
1 |
1 |
595 |
1 |
1 |
596 |
0 |
1 |
597 |
0 |
1 |
598 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
|
|
|
MISSING_ELSE |
602 |
1 |
1 |
603 |
1 |
1 |
604 |
1 |
1 |
605 |
1 |
1 |
606 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
636 |
1 |
1 |
641 |
1 |
1 |
642 |
1 |
1 |
646 |
1 |
1 |
652 |
1 |
1 |
675 |
1 |
1 |
678 |
1 |
1 |
680 |
1 |
1 |
709 |
1 |
1 |
743 |
1 |
1 |
750 |
3 |
3 |
753 |
1 |
1 |
754 |
1 |
1 |
756 |
1 |
1 |
758 |
1 |
1 |
759 |
1 |
1 |
Line Coverage for Module :
otp_ctrl_part_buf ( parameter Info=-1,CntWidth=3,DigestOffset=1776,StateWidth=12 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 160 | 147 | 91.88 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
ALWAYS | 206 | 140 | 127 | 90.71 |
CONT_ASSIGN | 636 | 1 | 1 | 100.00 |
CONT_ASSIGN | 641 | 1 | 1 | 100.00 |
CONT_ASSIGN | 642 | 1 | 1 | 100.00 |
CONT_ASSIGN | 646 | 1 | 1 | 100.00 |
CONT_ASSIGN | 652 | 1 | 1 | 100.00 |
CONT_ASSIGN | 675 | 1 | 1 | 100.00 |
CONT_ASSIGN | 678 | 1 | 1 | 100.00 |
CONT_ASSIGN | 680 | 1 | 1 | 100.00 |
CONT_ASSIGN | 709 | 1 | 1 | 100.00 |
CONT_ASSIGN | 729 | 1 | 1 | 100.00 |
ALWAYS | 750 | 3 | 3 | 100.00 |
ALWAYS | 753 | 5 | 5 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
182 |
1 |
1 |
193 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
212 |
1 |
1 |
215 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
224 |
1 |
1 |
225 |
1 |
1 |
226 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
237 |
1 |
1 |
238 |
1 |
1 |
240 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
254 |
1 |
1 |
255 |
1 |
1 |
256 |
1 |
1 |
|
|
|
MISSING_ELSE |
265 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
271 |
1 |
1 |
272 |
1 |
1 |
275 |
1 |
1 |
276 |
1 |
1 |
278 |
|
unreachable |
279 |
|
unreachable |
282 |
1 |
1 |
283 |
1 |
1 |
|
|
|
MISSING_ELSE |
286 |
1 |
1 |
287 |
1 |
1 |
|
|
|
MISSING_ELSE |
298 |
1 |
1 |
299 |
1 |
1 |
300 |
1 |
1 |
301 |
1 |
1 |
302 |
1 |
1 |
303 |
1 |
1 |
|
|
|
MISSING_ELSE |
311 |
1 |
1 |
312 |
1 |
1 |
313 |
1 |
1 |
314 |
1 |
1 |
315 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
|
|
|
MISSING_ELSE |
324 |
1 |
1 |
325 |
1 |
1 |
326 |
1 |
1 |
331 |
|
unreachable |
333 |
1 |
1 |
334 |
1 |
1 |
335 |
1 |
1 |
|
|
|
MISSING_ELSE |
343 |
1 |
1 |
348 |
1 |
1 |
349 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
351 |
1 |
1 |
352 |
1 |
1 |
|
|
|
MISSING_ELSE |
362 |
1 |
1 |
363 |
1 |
1 |
366 |
1 |
1 |
368 |
1 |
1 |
369 |
1 |
1 |
370 |
1 |
1 |
373 |
0 |
1 |
374 |
0 |
1 |
376 |
0 |
1 |
381 |
|
unreachable |
385 |
|
unreachable |
386 |
|
unreachable |
387 |
|
unreachable |
390 |
|
unreachable |
391 |
|
unreachable |
394 |
|
unreachable |
395 |
|
unreachable |
397 |
|
unreachable |
401 |
1 |
1 |
402 |
1 |
1 |
|
|
|
MISSING_ELSE |
405 |
1 |
1 |
406 |
1 |
1 |
408 |
1 |
1 |
|
|
|
MISSING_ELSE |
417 |
1 |
1 |
418 |
1 |
1 |
419 |
1 |
1 |
420 |
1 |
1 |
423 |
1 |
1 |
424 |
1 |
1 |
425 |
1 |
1 |
426 |
1 |
1 |
427 |
1 |
1 |
|
|
|
MISSING_ELSE |
432 |
|
unreachable |
433 |
|
unreachable |
434 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
443 |
|
unreachable |
444 |
|
unreachable |
445 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
455 |
1 |
1 |
456 |
1 |
1 |
457 |
1 |
1 |
458 |
1 |
1 |
459 |
1 |
1 |
460 |
1 |
1 |
|
|
|
MISSING_ELSE |
467 |
1 |
1 |
468 |
1 |
1 |
469 |
1 |
1 |
470 |
1 |
1 |
|
|
|
MISSING_ELSE |
480 |
1 |
1 |
481 |
1 |
1 |
482 |
1 |
1 |
483 |
1 |
1 |
485 |
1 |
1 |
489 |
1 |
1 |
490 |
1 |
1 |
491 |
1 |
1 |
493 |
0 |
1 |
494 |
0 |
1 |
498 |
1 |
1 |
499 |
1 |
1 |
|
|
|
MISSING_ELSE |
503 |
1 |
1 |
504 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
|
|
|
==> MISSING_ELSE |
516 |
0 |
1 |
517 |
0 |
1 |
518 |
0 |
1 |
519 |
0 |
1 |
520 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
528 |
1 |
1 |
529 |
1 |
1 |
530 |
1 |
1 |
531 |
1 |
1 |
532 |
1 |
1 |
|
|
|
MISSING_ELSE |
542 |
1 |
1 |
543 |
1 |
1 |
544 |
1 |
1 |
547 |
1 |
1 |
548 |
1 |
1 |
551 |
1 |
1 |
552 |
1 |
1 |
556 |
1 |
1 |
560 |
1 |
1 |
561 |
1 |
1 |
563 |
1 |
1 |
|
|
|
MISSING_ELSE |
572 |
1 |
1 |
573 |
1 |
1 |
574 |
1 |
1 |
|
|
|
MISSING_ELSE |
578 |
1 |
1 |
579 |
1 |
1 |
595 |
1 |
1 |
596 |
0 |
1 |
597 |
0 |
1 |
598 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
|
|
|
MISSING_ELSE |
602 |
1 |
1 |
603 |
1 |
1 |
604 |
1 |
1 |
605 |
1 |
1 |
606 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
636 |
1 |
1 |
641 |
1 |
1 |
642 |
1 |
1 |
646 |
1 |
1 |
652 |
1 |
1 |
675 |
1 |
1 |
678 |
1 |
1 |
680 |
1 |
1 |
709 |
1 |
1 |
729 |
1 |
1 |
750 |
3 |
3 |
753 |
1 |
1 |
754 |
1 |
1 |
756 |
1 |
1 |
758 |
1 |
1 |
759 |
1 |
1 |
Line Coverage for Module :
otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=1864,StateWidth=12 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 160 | 144 | 90.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
ALWAYS | 206 | 140 | 124 | 88.57 |
CONT_ASSIGN | 636 | 1 | 1 | 100.00 |
CONT_ASSIGN | 641 | 1 | 1 | 100.00 |
CONT_ASSIGN | 642 | 1 | 1 | 100.00 |
CONT_ASSIGN | 646 | 1 | 1 | 100.00 |
CONT_ASSIGN | 652 | 1 | 1 | 100.00 |
CONT_ASSIGN | 675 | 1 | 1 | 100.00 |
CONT_ASSIGN | 678 | 1 | 1 | 100.00 |
CONT_ASSIGN | 680 | 1 | 1 | 100.00 |
CONT_ASSIGN | 709 | 1 | 1 | 100.00 |
CONT_ASSIGN | 729 | 1 | 1 | 100.00 |
ALWAYS | 750 | 3 | 3 | 100.00 |
ALWAYS | 753 | 5 | 5 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
182 |
1 |
1 |
193 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
212 |
1 |
1 |
215 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
224 |
1 |
1 |
225 |
1 |
1 |
226 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
237 |
1 |
1 |
238 |
1 |
1 |
240 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
254 |
1 |
1 |
255 |
1 |
1 |
256 |
1 |
1 |
|
|
|
MISSING_ELSE |
265 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
271 |
1 |
1 |
272 |
1 |
1 |
275 |
1 |
1 |
276 |
1 |
1 |
278 |
|
unreachable |
279 |
|
unreachable |
282 |
1 |
1 |
283 |
1 |
1 |
|
|
|
MISSING_ELSE |
286 |
1 |
1 |
287 |
1 |
1 |
|
|
|
MISSING_ELSE |
298 |
1 |
1 |
299 |
1 |
1 |
300 |
1 |
1 |
301 |
1 |
1 |
302 |
1 |
1 |
303 |
1 |
1 |
|
|
|
MISSING_ELSE |
311 |
1 |
1 |
312 |
1 |
1 |
313 |
1 |
1 |
314 |
1 |
1 |
315 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
|
|
|
MISSING_ELSE |
324 |
1 |
1 |
325 |
1 |
1 |
326 |
1 |
1 |
331 |
|
unreachable |
333 |
1 |
1 |
334 |
1 |
1 |
335 |
1 |
1 |
|
|
|
MISSING_ELSE |
343 |
1 |
1 |
348 |
1 |
1 |
349 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
351 |
1 |
1 |
352 |
1 |
1 |
|
|
|
MISSING_ELSE |
362 |
1 |
1 |
363 |
1 |
1 |
366 |
1 |
1 |
368 |
1 |
1 |
369 |
1 |
1 |
370 |
1 |
1 |
373 |
0 |
1 |
374 |
0 |
1 |
376 |
0 |
1 |
381 |
|
unreachable |
385 |
|
unreachable |
386 |
|
unreachable |
387 |
|
unreachable |
390 |
|
unreachable |
391 |
|
unreachable |
394 |
|
unreachable |
395 |
|
unreachable |
397 |
|
unreachable |
401 |
1 |
1 |
402 |
1 |
1 |
|
|
|
MISSING_ELSE |
405 |
1 |
1 |
406 |
1 |
1 |
408 |
1 |
1 |
|
|
|
MISSING_ELSE |
417 |
1 |
1 |
418 |
1 |
1 |
419 |
1 |
1 |
420 |
1 |
1 |
423 |
1 |
1 |
424 |
1 |
1 |
425 |
1 |
1 |
426 |
1 |
1 |
427 |
1 |
1 |
|
|
|
MISSING_ELSE |
432 |
|
unreachable |
433 |
|
unreachable |
434 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
443 |
|
unreachable |
444 |
|
unreachable |
445 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
455 |
1 |
1 |
456 |
1 |
1 |
457 |
1 |
1 |
458 |
1 |
1 |
459 |
1 |
1 |
460 |
1 |
1 |
|
|
|
MISSING_ELSE |
467 |
1 |
1 |
468 |
1 |
1 |
469 |
1 |
1 |
470 |
1 |
1 |
|
|
|
MISSING_ELSE |
480 |
1 |
1 |
481 |
1 |
1 |
482 |
1 |
1 |
483 |
1 |
1 |
485 |
1 |
1 |
489 |
1 |
1 |
490 |
1 |
1 |
491 |
1 |
1 |
493 |
0 |
1 |
494 |
0 |
1 |
498 |
1 |
1 |
499 |
1 |
1 |
|
|
|
MISSING_ELSE |
503 |
1 |
1 |
504 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
|
|
|
==> MISSING_ELSE |
516 |
0 |
1 |
517 |
0 |
1 |
518 |
0 |
1 |
519 |
0 |
1 |
520 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
528 |
1 |
1 |
529 |
1 |
1 |
530 |
1 |
1 |
531 |
1 |
1 |
532 |
1 |
1 |
|
|
|
MISSING_ELSE |
542 |
1 |
1 |
543 |
1 |
1 |
544 |
1 |
1 |
547 |
1 |
1 |
548 |
1 |
1 |
551 |
1 |
1 |
552 |
1 |
1 |
556 |
1 |
1 |
560 |
0 |
1 |
561 |
0 |
1 |
563 |
0 |
1 |
|
|
|
MISSING_ELSE |
572 |
1 |
1 |
573 |
1 |
1 |
574 |
1 |
1 |
|
|
|
MISSING_ELSE |
578 |
1 |
1 |
579 |
1 |
1 |
595 |
1 |
1 |
596 |
0 |
1 |
597 |
0 |
1 |
598 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
|
|
|
MISSING_ELSE |
602 |
1 |
1 |
603 |
1 |
1 |
604 |
1 |
1 |
605 |
1 |
1 |
606 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
636 |
1 |
1 |
641 |
1 |
1 |
642 |
1 |
1 |
646 |
1 |
1 |
652 |
1 |
1 |
675 |
1 |
1 |
678 |
1 |
1 |
680 |
1 |
1 |
709 |
1 |
1 |
729 |
1 |
1 |
750 |
3 |
3 |
753 |
1 |
1 |
754 |
1 |
1 |
756 |
1 |
1 |
758 |
1 |
1 |
759 |
1 |
1 |
Line Coverage for Module :
otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=1952,StateWidth=12 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 160 | 147 | 91.88 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
ALWAYS | 206 | 140 | 127 | 90.71 |
CONT_ASSIGN | 636 | 1 | 1 | 100.00 |
CONT_ASSIGN | 641 | 1 | 1 | 100.00 |
CONT_ASSIGN | 642 | 1 | 1 | 100.00 |
CONT_ASSIGN | 646 | 1 | 1 | 100.00 |
CONT_ASSIGN | 652 | 1 | 1 | 100.00 |
CONT_ASSIGN | 675 | 1 | 1 | 100.00 |
CONT_ASSIGN | 678 | 1 | 1 | 100.00 |
CONT_ASSIGN | 680 | 1 | 1 | 100.00 |
CONT_ASSIGN | 709 | 1 | 1 | 100.00 |
CONT_ASSIGN | 729 | 1 | 1 | 100.00 |
ALWAYS | 750 | 3 | 3 | 100.00 |
ALWAYS | 753 | 5 | 5 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
182 |
1 |
1 |
193 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
212 |
1 |
1 |
215 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
224 |
1 |
1 |
225 |
1 |
1 |
226 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
237 |
1 |
1 |
238 |
1 |
1 |
240 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
254 |
1 |
1 |
255 |
1 |
1 |
256 |
1 |
1 |
|
|
|
MISSING_ELSE |
265 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
271 |
1 |
1 |
272 |
1 |
1 |
275 |
1 |
1 |
276 |
1 |
1 |
278 |
|
unreachable |
279 |
|
unreachable |
282 |
1 |
1 |
283 |
1 |
1 |
|
|
|
MISSING_ELSE |
286 |
1 |
1 |
287 |
1 |
1 |
|
|
|
MISSING_ELSE |
298 |
1 |
1 |
299 |
1 |
1 |
300 |
1 |
1 |
301 |
1 |
1 |
302 |
1 |
1 |
303 |
1 |
1 |
|
|
|
MISSING_ELSE |
311 |
1 |
1 |
312 |
1 |
1 |
313 |
1 |
1 |
314 |
1 |
1 |
315 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
|
|
|
MISSING_ELSE |
324 |
1 |
1 |
325 |
1 |
1 |
326 |
1 |
1 |
331 |
|
unreachable |
333 |
1 |
1 |
334 |
1 |
1 |
335 |
1 |
1 |
|
|
|
MISSING_ELSE |
343 |
1 |
1 |
348 |
1 |
1 |
349 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
351 |
1 |
1 |
352 |
1 |
1 |
|
|
|
MISSING_ELSE |
362 |
1 |
1 |
363 |
1 |
1 |
366 |
1 |
1 |
368 |
1 |
1 |
369 |
1 |
1 |
370 |
1 |
1 |
373 |
0 |
1 |
374 |
0 |
1 |
376 |
0 |
1 |
381 |
|
unreachable |
385 |
|
unreachable |
386 |
|
unreachable |
387 |
|
unreachable |
390 |
|
unreachable |
391 |
|
unreachable |
394 |
|
unreachable |
395 |
|
unreachable |
397 |
|
unreachable |
401 |
1 |
1 |
402 |
1 |
1 |
|
|
|
MISSING_ELSE |
405 |
1 |
1 |
406 |
1 |
1 |
408 |
1 |
1 |
|
|
|
MISSING_ELSE |
417 |
1 |
1 |
418 |
1 |
1 |
419 |
1 |
1 |
420 |
1 |
1 |
423 |
1 |
1 |
424 |
1 |
1 |
425 |
1 |
1 |
426 |
1 |
1 |
427 |
1 |
1 |
|
|
|
MISSING_ELSE |
432 |
|
unreachable |
433 |
|
unreachable |
434 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
443 |
|
unreachable |
444 |
|
unreachable |
445 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
455 |
1 |
1 |
456 |
1 |
1 |
457 |
1 |
1 |
458 |
1 |
1 |
459 |
1 |
1 |
460 |
1 |
1 |
|
|
|
MISSING_ELSE |
467 |
1 |
1 |
468 |
1 |
1 |
469 |
1 |
1 |
470 |
1 |
1 |
|
|
|
MISSING_ELSE |
480 |
1 |
1 |
481 |
1 |
1 |
482 |
1 |
1 |
483 |
1 |
1 |
485 |
1 |
1 |
489 |
1 |
1 |
490 |
1 |
1 |
491 |
1 |
1 |
493 |
0 |
1 |
494 |
0 |
1 |
498 |
1 |
1 |
499 |
1 |
1 |
|
|
|
MISSING_ELSE |
503 |
1 |
1 |
504 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
|
|
|
==> MISSING_ELSE |
516 |
0 |
1 |
517 |
0 |
1 |
518 |
0 |
1 |
519 |
0 |
1 |
520 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
528 |
1 |
1 |
529 |
1 |
1 |
530 |
1 |
1 |
531 |
1 |
1 |
532 |
1 |
1 |
|
|
|
MISSING_ELSE |
542 |
1 |
1 |
543 |
1 |
1 |
544 |
1 |
1 |
547 |
1 |
1 |
548 |
1 |
1 |
551 |
1 |
1 |
552 |
1 |
1 |
556 |
1 |
1 |
560 |
1 |
1 |
561 |
1 |
1 |
563 |
1 |
1 |
|
|
|
MISSING_ELSE |
572 |
1 |
1 |
573 |
1 |
1 |
574 |
1 |
1 |
|
|
|
MISSING_ELSE |
578 |
1 |
1 |
579 |
1 |
1 |
595 |
1 |
1 |
596 |
0 |
1 |
597 |
0 |
1 |
598 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
|
|
|
MISSING_ELSE |
602 |
1 |
1 |
603 |
1 |
1 |
604 |
1 |
1 |
605 |
1 |
1 |
606 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
636 |
1 |
1 |
641 |
1 |
1 |
642 |
1 |
1 |
646 |
1 |
1 |
652 |
1 |
1 |
675 |
1 |
1 |
678 |
1 |
1 |
680 |
1 |
1 |
709 |
1 |
1 |
729 |
1 |
1 |
750 |
3 |
3 |
753 |
1 |
1 |
754 |
1 |
1 |
756 |
1 |
1 |
758 |
1 |
1 |
759 |
1 |
1 |
Line Coverage for Module :
otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=2040,StateWidth=12 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 131 | 94 | 71.76 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 193 | 1 | 1 | 100.00 |
ALWAYS | 206 | 111 | 77 | 69.37 |
CONT_ASSIGN | 636 | 1 | 0 | 0.00 |
CONT_ASSIGN | 641 | 1 | 1 | 100.00 |
CONT_ASSIGN | 642 | 1 | 1 | 100.00 |
CONT_ASSIGN | 646 | 1 | 1 | 100.00 |
CONT_ASSIGN | 652 | 1 | 1 | 100.00 |
CONT_ASSIGN | 675 | 1 | 1 | 100.00 |
CONT_ASSIGN | 678 | 1 | 1 | 100.00 |
CONT_ASSIGN | 680 | 1 | 1 | 100.00 |
CONT_ASSIGN | 723 | 1 | 0 | 0.00 |
CONT_ASSIGN | 743 | 1 | 0 | 0.00 |
ALWAYS | 750 | 3 | 3 | 100.00 |
ALWAYS | 753 | 5 | 5 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
182 |
1 |
1 |
193 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
212 |
1 |
1 |
215 |
1 |
1 |
218 |
1 |
1 |
219 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
224 |
1 |
1 |
225 |
1 |
1 |
226 |
1 |
1 |
229 |
1 |
1 |
230 |
1 |
1 |
233 |
1 |
1 |
234 |
1 |
1 |
237 |
1 |
1 |
238 |
1 |
1 |
240 |
1 |
1 |
245 |
1 |
1 |
246 |
1 |
1 |
|
|
|
MISSING_ELSE |
254 |
1 |
1 |
255 |
1 |
1 |
256 |
1 |
1 |
|
|
|
MISSING_ELSE |
265 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
271 |
1 |
1 |
272 |
1 |
1 |
275 |
1 |
1 |
276 |
|
unreachable |
278 |
1 |
1 |
279 |
1 |
1 |
282 |
1 |
1 |
283 |
1 |
1 |
|
|
|
MISSING_ELSE |
286 |
1 |
1 |
287 |
1 |
1 |
|
|
|
MISSING_ELSE |
298 |
0 |
1 |
299 |
0 |
1 |
300 |
0 |
1 |
301 |
0 |
1 |
302 |
0 |
1 |
303 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
311 |
0 |
1 |
312 |
0 |
1 |
313 |
0 |
1 |
314 |
0 |
1 |
315 |
|
unreachable |
316 |
|
unreachable |
317 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
324 |
1 |
1 |
325 |
1 |
1 |
326 |
|
unreachable |
331 |
1 |
1 |
333 |
1 |
1 |
334 |
1 |
1 |
335 |
1 |
1 |
|
|
|
MISSING_ELSE |
343 |
1 |
1 |
348 |
1 |
1 |
349 |
|
unreachable |
|
|
|
MISSING_ELSE |
351 |
1 |
1 |
352 |
1 |
1 |
|
|
|
MISSING_ELSE |
362 |
1 |
1 |
363 |
1 |
1 |
366 |
1 |
1 |
368 |
|
unreachable |
369 |
|
unreachable |
370 |
|
unreachable |
373 |
|
unreachable |
374 |
|
unreachable |
376 |
|
unreachable |
381 |
1 |
1 |
385 |
1 |
1 |
386 |
1 |
1 |
387 |
1 |
1 |
390 |
1 |
1 |
391 |
1 |
1 |
394 |
1 |
1 |
395 |
1 |
1 |
397 |
1 |
1 |
401 |
1 |
1 |
402 |
1 |
1 |
|
|
|
MISSING_ELSE |
405 |
1 |
1 |
406 |
1 |
1 |
408 |
1 |
1 |
|
|
|
MISSING_ELSE |
417 |
1 |
1 |
418 |
|
unreachable |
419 |
|
unreachable |
420 |
|
unreachable |
423 |
|
unreachable |
424 |
|
unreachable |
425 |
|
unreachable |
426 |
|
unreachable |
427 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
432 |
|
unreachable |
433 |
|
unreachable |
434 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
443 |
1 |
1 |
444 |
1 |
1 |
445 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
455 |
0 |
1 |
456 |
0 |
1 |
457 |
0 |
1 |
458 |
0 |
1 |
459 |
0 |
1 |
460 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
467 |
0 |
1 |
468 |
0 |
1 |
469 |
0 |
1 |
470 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
480 |
0 |
1 |
481 |
0 |
1 |
482 |
0 |
1 |
483 |
|
unreachable |
485 |
|
unreachable |
489 |
|
unreachable |
490 |
|
unreachable |
491 |
|
unreachable |
493 |
|
unreachable |
494 |
|
unreachable |
498 |
|
unreachable |
499 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
503 |
|
unreachable |
504 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
|
|
|
==> MISSING_ELSE |
516 |
0 |
1 |
517 |
0 |
1 |
518 |
0 |
1 |
519 |
0 |
1 |
520 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
528 |
0 |
1 |
529 |
0 |
1 |
530 |
0 |
1 |
531 |
0 |
1 |
532 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
542 |
0 |
1 |
543 |
0 |
1 |
544 |
0 |
1 |
547 |
|
unreachable |
548 |
|
unreachable |
551 |
|
unreachable |
552 |
|
unreachable |
556 |
|
unreachable |
560 |
|
unreachable |
561 |
|
unreachable |
563 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
572 |
1 |
1 |
573 |
1 |
1 |
574 |
1 |
1 |
|
|
|
MISSING_ELSE |
578 |
1 |
1 |
579 |
1 |
1 |
595 |
1 |
1 |
596 |
0 |
1 |
597 |
0 |
1 |
598 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
|
|
|
MISSING_ELSE |
602 |
1 |
1 |
603 |
1 |
1 |
604 |
1 |
1 |
605 |
1 |
1 |
606 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
636 |
0 |
1 |
641 |
1 |
1 |
642 |
1 |
1 |
646 |
1 |
1 |
652 |
1 |
1 |
675 |
1 |
1 |
678 |
1 |
1 |
680 |
1 |
1 |
723 |
0 |
1 |
743 |
0 |
1 |
750 |
3 |
3 |
753 |
1 |
1 |
754 |
1 |
1 |
756 |
1 |
1 |
758 |
1 |
1 |
759 |
1 |
1 |
Cond Coverage for Module :
otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=1720,StateWidth=12 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 48 | 41 | 85.42 |
Logical | 48 | 41 | 85.42 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 271
EXPRESSION (cnt == LastScrmblBlock)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 282
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T23,T24,T25 |
LINE 302
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 368
EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
-----------1---------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T26 |
0 | 1 | Covered | T4,T12,T15 |
1 | 0 | Covered | T27,T7,T28 |
LINE 368
SUB-EXPRESSION (digest_o == data_mux)
-----------1----------
-1- | Status | Tests |
0 | Covered | T4,T12,T15 |
1 | Covered | T2,T3,T6 |
LINE 368
SUB-EXPRESSION (digest_o == '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T27,T7,T28 |
1 | Covered | T2,T3,T4 |
LINE 385
EXPRESSION (cnt == LastScrmblBlock)
------------1-----------
-1- | Status | Tests |
0 | Unreachable | |
1 | Unreachable | |
LINE 401
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T3,T4 |
1 | Covered | T29,T30,T31 |
LINE 426
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 433
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 485
EXPRESSION (cnt == PenultimateScrmblBlock)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 547
EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
-----------1---------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T32,T33,T34 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T35,T27,T13 |
LINE 547
SUB-EXPRESSION (digest_o == data_mux)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T35,T27,T13 |
LINE 547
SUB-EXPRESSION (digest_o == '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T35,T27,T13 |
1 | Covered | T1,T2,T3 |
LINE 573
EXPRESSION (error_q == NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T20,T21,T22 |
LINE 597
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 605
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 636
EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11001111000)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T4 |
LINE 636
SUB-EXPRESSION (base_sel == DigOffset)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T4 |
LINE 652
EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 652
SUB-EXPRESSION (data_sel == ScrmblData)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 678
EXPRESSION (init_done_o ? data : DataDefault)
-----1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 709
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T35,T27,T13 |
LINE 709
SUB-EXPRESSION (digest_o != '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T35,T27,T13 |
Cond Coverage for Module :
otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=1952,StateWidth=12 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 52 | 45 | 86.54 |
Logical | 52 | 45 | 86.54 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 271
EXPRESSION (cnt == LastScrmblBlock)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 282
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T26,T36,T37 |
LINE 302
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 368
EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
-----------1---------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T16,T38,T39 |
1 | 0 | Covered | T27,T7,T28 |
LINE 368
SUB-EXPRESSION (digest_o == data_mux)
-----------1----------
-1- | Status | Tests |
0 | Covered | T16,T38,T39 |
1 | Covered | T2,T3,T4 |
LINE 368
SUB-EXPRESSION (digest_o == '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T27,T7,T28 |
1 | Covered | T2,T3,T4 |
LINE 385
EXPRESSION (cnt == LastScrmblBlock)
------------1-----------
-1- | Status | Tests |
0 | Unreachable | |
1 | Unreachable | |
LINE 401
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T3,T4 |
1 | Covered | T27,T40,T41 |
LINE 426
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 433
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 485
EXPRESSION (cnt == PenultimateScrmblBlock)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 547
EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
-----------1---------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T42 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T27,T7,T28 |
LINE 547
SUB-EXPRESSION (digest_o == data_mux)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T27,T7,T28 |
LINE 547
SUB-EXPRESSION (digest_o == '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T27,T7,T28 |
1 | Covered | T1,T2,T3 |
LINE 573
EXPRESSION (error_q == NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T20,T21,T22 |
LINE 597
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 605
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 636
EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11101010000)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T4 |
LINE 636
SUB-EXPRESSION (base_sel == DigOffset)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T4 |
LINE 652
EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 652
SUB-EXPRESSION (data_sel == ScrmblData)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 678
EXPRESSION (init_done_o ? data : DataDefault)
-----1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 709
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T27,T7,T28 |
LINE 709
SUB-EXPRESSION (digest_o != '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T27,T7,T28 |
LINE 729
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T27,T7,T28 |
LINE 729
SUB-EXPRESSION (digest_o != '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T27,T7,T28 |
Cond Coverage for Module :
otp_ctrl_part_buf ( parameter Info=-1,CntWidth=1,DigestOffset=1736,StateWidth=12 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 48 | 39 | 81.25 |
Logical | 48 | 39 | 81.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 271
EXPRESSION (cnt == LastScrmblBlock)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 282
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T11,T43,T44 |
LINE 302
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 368
EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
-----------1---------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T4,T12,T15 |
1 | 0 | Covered | T27,T7,T28 |
LINE 368
SUB-EXPRESSION (digest_o == data_mux)
-----------1----------
-1- | Status | Tests |
0 | Covered | T4,T12,T15 |
1 | Covered | T2,T3,T6 |
LINE 368
SUB-EXPRESSION (digest_o == '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T27,T7,T28 |
1 | Covered | T2,T3,T4 |
LINE 385
EXPRESSION (cnt == LastScrmblBlock)
------------1-----------
-1- | Status | Tests |
0 | Unreachable | |
1 | Unreachable | |
LINE 401
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T3,T4 |
1 | Covered | T45,T46 |
LINE 426
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 433
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 485
EXPRESSION (cnt == PenultimateScrmblBlock)
---------------1---------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 547
EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
-----------1---------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T47,T48,T49 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T35,T27 |
LINE 547
SUB-EXPRESSION (digest_o == data_mux)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T35,T27 |
LINE 547
SUB-EXPRESSION (digest_o == '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T3,T35,T27 |
1 | Covered | T1,T2,T3 |
LINE 573
EXPRESSION (error_q == NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T20,T21,T22 |
LINE 597
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 605
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 636
EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11011000000)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T4 |
LINE 636
SUB-EXPRESSION (base_sel == DigOffset)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T4 |
LINE 652
EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 652
SUB-EXPRESSION (data_sel == ScrmblData)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 678
EXPRESSION (init_done_o ? data : DataDefault)
-----1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 709
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T35,T27 |
LINE 709
SUB-EXPRESSION (digest_o != '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T35,T27 |
Cond Coverage for Module :
otp_ctrl_part_buf ( parameter Info=-1,CntWidth=3,DigestOffset=1776,StateWidth=12 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 52 | 45 | 86.54 |
Logical | 52 | 45 | 86.54 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 271
EXPRESSION (cnt == LastScrmblBlock)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 282
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T50,T51,T52 |
LINE 302
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 368
EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
-----------1---------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T4,T12,T15 |
1 | 0 | Covered | T27,T7,T28 |
LINE 368
SUB-EXPRESSION (digest_o == data_mux)
-----------1----------
-1- | Status | Tests |
0 | Covered | T4,T12,T15 |
1 | Covered | T2,T3,T6 |
LINE 368
SUB-EXPRESSION (digest_o == '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T27,T7,T28 |
1 | Covered | T2,T3,T4 |
LINE 385
EXPRESSION (cnt == LastScrmblBlock)
------------1-----------
-1- | Status | Tests |
0 | Unreachable | |
1 | Unreachable | |
LINE 401
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T3,T4 |
1 | Covered | T53,T54 |
LINE 426
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 433
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 485
EXPRESSION (cnt == PenultimateScrmblBlock)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 547
EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
-----------1---------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T55,T56,T57 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T27,T13,T7 |
LINE 547
SUB-EXPRESSION (digest_o == data_mux)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T27,T13,T7 |
LINE 547
SUB-EXPRESSION (digest_o == '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T27,T13,T7 |
1 | Covered | T1,T2,T3 |
LINE 573
EXPRESSION (error_q == NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T20,T21,T22 |
LINE 597
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 605
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 636
EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11011010000)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T4 |
LINE 636
SUB-EXPRESSION (base_sel == DigOffset)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T4 |
LINE 652
EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 652
SUB-EXPRESSION (data_sel == ScrmblData)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 678
EXPRESSION (init_done_o ? data : DataDefault)
-----1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 709
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T27,T13,T7 |
LINE 709
SUB-EXPRESSION (digest_o != '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T27,T13,T7 |
LINE 729
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T27,T13,T7 |
LINE 729
SUB-EXPRESSION (digest_o != '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T27,T13,T7 |
Cond Coverage for Module :
otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=2040,StateWidth=12 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 24 | 18 | 75.00 |
Logical | 24 | 18 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 271
EXPRESSION (cnt == LastScrmblBlock)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 282
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T23,T58,T51 |
LINE 302
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 368
EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
-----------1---------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Unreachable | |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 368
SUB-EXPRESSION (digest_o == data_mux)
-----------1----------
-1- | Status | Tests |
0 | Unreachable | |
1 | Unreachable | |
LINE 368
SUB-EXPRESSION (digest_o == '0)
--------1-------
-1- | Status | Tests |
0 | Unreachable | |
1 | Unreachable | |
LINE 385
EXPRESSION (cnt == LastScrmblBlock)
------------1-----------
-1- | Status | Tests |
0 | Covered | T2,T3,T4 |
1 | Covered | T2,T3,T4 |
LINE 401
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T3,T4 |
1 | Covered | T59,T60 |
LINE 426
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 433
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 485
EXPRESSION (cnt == PenultimateScrmblBlock)
---------------1---------------
-1- | Status | Tests |
0 | Unreachable | |
1 | Unreachable | |
LINE 547
EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
-----------1---------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Unreachable | |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 547
SUB-EXPRESSION (digest_o == data_mux)
-----------1----------
-1- | Status | Tests |
0 | Unreachable | |
1 | Unreachable | |
LINE 547
SUB-EXPRESSION (digest_o == '0)
--------1-------
-1- | Status | Tests |
0 | Unreachable | |
1 | Unreachable | |
LINE 573
EXPRESSION (error_q == NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T20,T21,T22 |
LINE 597
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 605
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 636
EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11110101000)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 636
SUB-EXPRESSION (base_sel == DigOffset)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 652
EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 652
SUB-EXPRESSION (data_sel == ScrmblData)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 678
EXPRESSION (init_done_o ? data : DataDefault)
-----1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=1864,StateWidth=12 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 52 | 44 | 84.62 |
Logical | 52 | 44 | 84.62 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 271
EXPRESSION (cnt == LastScrmblBlock)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 282
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T61,T26,T37 |
LINE 302
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 368
EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
-----------1---------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T4,T12,T15 |
1 | 0 | Covered | T27,T7,T28 |
LINE 368
SUB-EXPRESSION (digest_o == data_mux)
-----------1----------
-1- | Status | Tests |
0 | Covered | T4,T12,T15 |
1 | Covered | T2,T3,T6 |
LINE 368
SUB-EXPRESSION (digest_o == '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T27,T7,T28 |
1 | Covered | T2,T3,T4 |
LINE 385
EXPRESSION (cnt == LastScrmblBlock)
------------1-----------
-1- | Status | Tests |
0 | Unreachable | |
1 | Unreachable | |
LINE 401
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T3,T4 |
1 | Covered | T27,T62,T63 |
LINE 426
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 433
EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
--------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 485
EXPRESSION (cnt == PenultimateScrmblBlock)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 547
EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
-----------1---------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T35,T27,T7 |
LINE 547
SUB-EXPRESSION (digest_o == data_mux)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T35,T27,T7 |
LINE 547
SUB-EXPRESSION (digest_o == '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T35,T27,T7 |
1 | Covered | T1,T2,T3 |
LINE 573
EXPRESSION (error_q == NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T20,T21,T22 |
LINE 597
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 605
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 636
EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11011111000)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T4 |
LINE 636
SUB-EXPRESSION (base_sel == DigOffset)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T4 |
LINE 652
EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 652
SUB-EXPRESSION (data_sel == ScrmblData)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 678
EXPRESSION (init_done_o ? data : DataDefault)
-----1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 709
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T35,T27,T7 |
LINE 709
SUB-EXPRESSION (digest_o != '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T35,T27,T7 |
LINE 729
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T35,T27,T7 |
LINE 729
SUB-EXPRESSION (digest_o != '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T35,T27,T7 |
FSM Coverage for Module :
otp_ctrl_part_buf
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
16 |
16 |
100.00 |
(Not included in score) |
Transitions |
38 |
37 |
97.37 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
CnstyReadSt |
334 |
Covered |
T2,T3,T4 |
CnstyReadWaitSt |
352 |
Covered |
T2,T3,T4 |
ErrorSt |
286 |
Covered |
T1,T2,T3 |
IdleSt |
369 |
Covered |
T1,T2,T3 |
InitDescrSt |
276 |
Covered |
T1,T2,T3 |
InitDescrWaitSt |
303 |
Covered |
T1,T2,T3 |
InitSt |
246 |
Covered |
T1,T2,T3 |
InitWaitSt |
256 |
Covered |
T1,T2,T3 |
IntegDigClrSt |
272 |
Covered |
T1,T2,T3 |
IntegDigFinSt |
491 |
Covered |
T1,T2,T3 |
IntegDigPadSt |
493 |
Covered |
T1,T2,T3 |
IntegDigSt |
434 |
Covered |
T1,T2,T3 |
IntegDigWaitSt |
532 |
Covered |
T1,T2,T3 |
IntegScrSt |
427 |
Covered |
T1,T2,T3 |
IntegScrWaitSt |
460 |
Covered |
T1,T2,T3 |
ResetSt |
244 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests |
CnstyReadSt->CnstyReadWaitSt |
352 |
Covered |
T2,T3,T4 |
CnstyReadSt->ErrorSt |
596 |
Covered |
T4,T12,T64 |
CnstyReadWaitSt->CnstyReadSt |
390 |
Covered |
T2,T3,T4 |
CnstyReadWaitSt->ErrorSt |
373 |
Covered |
T4,T12,T64 |
CnstyReadWaitSt->IdleSt |
369 |
Covered |
T2,T3,T4 |
IdleSt->CnstyReadSt |
334 |
Covered |
T2,T3,T4 |
IdleSt->ErrorSt |
596 |
Covered |
T1,T2,T3 |
IdleSt->IntegDigClrSt |
326 |
Covered |
T2,T3,T4 |
InitDescrSt->ErrorSt |
596 |
Covered |
T11,T55,T56 |
InitDescrSt->InitDescrWaitSt |
303 |
Covered |
T1,T2,T3 |
InitDescrWaitSt->ErrorSt |
596 |
Covered |
T11,T55,T56 |
InitDescrWaitSt->InitSt |
315 |
Covered |
T1,T2,T3 |
InitSt->ErrorSt |
596 |
Covered |
T5,T8,T10 |
InitSt->InitWaitSt |
256 |
Covered |
T1,T2,T3 |
InitWaitSt->ErrorSt |
286 |
Covered |
T5,T11,T43 |
InitWaitSt->InitDescrSt |
276 |
Covered |
T1,T2,T3 |
InitWaitSt->InitSt |
278 |
Covered |
T1,T2,T3 |
InitWaitSt->IntegDigClrSt |
272 |
Covered |
T1,T2,T3 |
IntegDigClrSt->ErrorSt |
596 |
Covered |
T3,T27,T7 |
IntegDigClrSt->IdleSt |
443 |
Covered |
T1,T2,T3 |
IntegDigClrSt->IntegDigSt |
434 |
Covered |
T1,T2,T3 |
IntegDigClrSt->IntegScrSt |
427 |
Covered |
T1,T2,T3 |
IntegDigFinSt->ErrorSt |
596 |
Covered |
T39,T65,T66 |
IntegDigFinSt->IntegDigWaitSt |
532 |
Covered |
T1,T2,T3 |
IntegDigPadSt->ErrorSt |
596 |
Not Covered |
|
IntegDigPadSt->IntegDigFinSt |
520 |
Covered |
T1,T2,T3 |
IntegDigSt->ErrorSt |
596 |
Covered |
T67,T39,T68 |
IntegDigSt->IntegDigFinSt |
491 |
Covered |
T1,T2,T3 |
IntegDigSt->IntegDigPadSt |
493 |
Covered |
T1,T2,T3 |
IntegDigSt->IntegScrSt |
504 |
Covered |
T1,T2,T3 |
IntegDigWaitSt->ErrorSt |
560 |
Covered |
T55,T47,T32 |
IntegDigWaitSt->IdleSt |
548 |
Covered |
T1,T2,T3 |
IntegScrSt->ErrorSt |
596 |
Covered |
T69,T70,T71 |
IntegScrSt->IntegScrWaitSt |
460 |
Covered |
T1,T2,T3 |
IntegScrWaitSt->ErrorSt |
596 |
Covered |
T3,T27,T7 |
IntegScrWaitSt->IntegDigSt |
470 |
Covered |
T1,T2,T3 |
ResetSt->ErrorSt |
596 |
Covered |
T72,T73,T74 |
ResetSt->InitSt |
246 |
Covered |
T1,T2,T3 |
Summary for FSM :: error_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
9 |
5 |
55.56 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: error_q
states | Line No. | Covered | Tests |
CheckFailError |
374 |
Covered |
T55,T56,T47 |
FsmStateError |
574 |
Covered |
T1,T2,T3 |
MacroEccCorrError |
283 |
Covered |
T11,T43,T29 |
NoError |
573 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests |
CheckFailError->FsmStateError |
606 |
Not Covered |
|
CheckFailError->MacroEccCorrError |
283 |
Not Covered |
|
FsmStateError->CheckFailError |
374 |
Not Covered |
|
FsmStateError->MacroEccCorrError |
283 |
Not Covered |
|
MacroEccCorrError->CheckFailError |
374 |
Covered |
T58,T51,T75 |
MacroEccCorrError->FsmStateError |
606 |
Covered |
T11,T43,T44 |
NoError->CheckFailError |
374 |
Covered |
T55,T56,T47 |
NoError->FsmStateError |
574 |
Covered |
T1,T2,T3 |
NoError->MacroEccCorrError |
283 |
Covered |
T11,T43,T29 |
Branch Coverage for Module :
otp_ctrl_part_buf ( parameter Info=-1,CntWidth=3,DigestOffset=1776,StateWidth=12 + Info=-1,CntWidth=4,DigestOffset=1864,StateWidth=12 + Info=-1,CntWidth=4,DigestOffset=1952,StateWidth=12 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
73 |
62 |
84.93 |
TERNARY |
636 |
2 |
2 |
100.00 |
TERNARY |
652 |
2 |
2 |
100.00 |
TERNARY |
678 |
2 |
2 |
100.00 |
TERNARY |
709 |
2 |
2 |
100.00 |
TERNARY |
729 |
2 |
2 |
100.00 |
CASE |
240 |
53 |
44 |
83.02 |
IF |
595 |
3 |
1 |
33.33 |
IF |
602 |
3 |
3 |
100.00 |
IF |
750 |
2 |
2 |
100.00 |
IF |
753 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 636 ((base_sel == DigOffset)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 652 ((data_sel == ScrmblData)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 678 (init_done_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 709 ((digest_o != '0)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T35,T27,T13 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 729 ((digest_o != '0)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T35,T27,T13 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 240 case (state_q)
-2-: 245 if (init_req_i)
-3-: 255 if (otp_gnt_i)
-4-: 265 if (otp_rvalid_i)
-5-: 267 if ((otp_err inside {NoError, MacroEccCorrError}))
-6-: 271 if ((cnt == LastScrmblBlock))
-7-: 275 if (1'b1)
-8-: 282 if ((otp_err != NoError))
-9-: 302 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-10-: 314 if (scrmbl_valid_i)
-11-: 324 if (integ_chk_req_i)
-12-: 325 if (1'b1)
-13-: 333 if (cnsty_chk_req_i)
-14-: 348 if (1'b1)
-15-: 351 if (otp_gnt_i)
-16-: 362 if (otp_rvalid_i)
-17-: 363 if ((otp_err inside {NoError, MacroEccCorrError}))
-18-: 366 if (1'b1)
-19-: 368 if (((digest_o == data_mux) || (digest_o == '0)))
-20-: 381 if (((scrmbl_data_o == data_mux) || lc_ctrl_pkg::lc_tx_test_true_strict(check_byp_en_i)))
-21-: 385 if ((cnt == LastScrmblBlock))
-22-: 401 if ((otp_err != NoError))
-23-: 417 if (1'b1)
-24-: 424 if (1'b1)
-25-: 426 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-26-: 433 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-27-: 444 if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-28-: 459 if (scrmbl_ready_i)
-29-: 469 if (scrmbl_valid_i)
-30-: 482 if (scrmbl_ready_i)
-31-: 485 if ((cnt == PenultimateScrmblBlock))
-32-: 489 if (cnt[0])
-33-: 498 if (cnt[0])
-34-: 503 if (1'b1)
-35-: 519 if (scrmbl_ready_i)
-36-: 531 if (scrmbl_ready_i)
-37-: 544 if (scrmbl_valid_i)
-38-: 547 if (((digest_o == data_mux) || (digest_o == '0)))
-39-: 551 if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-40-: 573 if ((error_q == NoError))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | -17- | -18- | -19- | -20- | -21- | -22- | -23- | -24- | -25- | -26- | -27- | -28- | -29- | -30- | -31- | -32- | -33- | -34- | -35- | -36- | -37- | -38- | -39- | -40- | Status | Tests |
ResetSt |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
ResetSt |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitSt |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitSt |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
1 |
1 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
1 |
1 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
InitWaitSt |
- |
- |
1 |
1 |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T50,T51,T52 |
InitWaitSt |
- |
- |
1 |
1 |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T43,T76,T77 |
InitWaitSt |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitDescrSt |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitDescrSt |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitDescrWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitDescrWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IdleSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
IdleSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
IdleSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
IdleSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
CnstyReadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
CnstyReadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
CnstyReadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
CnstyReadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T27,T62,T63 |
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T64,T78,T79 |
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
IntegDigClrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigClrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigClrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
IntegDigClrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IntegDigClrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
IntegDigClrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IntegScrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegScrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegScrWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegScrWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IntegDigPadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Not Covered |
|
IntegDigPadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Not Covered |
|
IntegDigFinSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigFinSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
Covered |
T1,T2,T3 |
IntegDigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
Covered |
T2,T3,T4 |
IntegDigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
Covered |
T55,T56,T57 |
IntegDigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T20,T21,T22 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T20,T21,T22 |
LineNo. Expression
-1-: 595 if (ecc_err)
-2-: 597 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Not Covered |
|
1 |
0 |
Not Covered |
|
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 602 if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-: 605 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T1,T2,T3 |
1 |
0 |
Covered |
T1,T2,T3 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 750 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 753 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=1720,StateWidth=12 + Info=-1,CntWidth=1,DigestOffset=1736,StateWidth=12 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
70 |
56 |
80.00 |
TERNARY |
636 |
2 |
2 |
100.00 |
TERNARY |
652 |
2 |
2 |
100.00 |
TERNARY |
678 |
2 |
2 |
100.00 |
TERNARY |
709 |
2 |
2 |
100.00 |
CASE |
240 |
52 |
40 |
76.92 |
IF |
595 |
3 |
1 |
33.33 |
IF |
602 |
3 |
3 |
100.00 |
IF |
750 |
2 |
2 |
100.00 |
IF |
753 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 636 ((base_sel == DigOffset)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 652 ((data_sel == ScrmblData)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 678 (init_done_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 709 ((digest_o != '0)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T35,T27 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 240 case (state_q)
-2-: 245 if (init_req_i)
-3-: 255 if (otp_gnt_i)
-4-: 265 if (otp_rvalid_i)
-5-: 267 if ((otp_err inside {NoError, MacroEccCorrError}))
-6-: 271 if ((cnt == LastScrmblBlock))
-7-: 275 if (1'b0)
-8-: 282 if ((otp_err != NoError))
-9-: 302 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-10-: 314 if (scrmbl_valid_i)
-11-: 324 if (integ_chk_req_i)
-12-: 325 if (1'b1)
-13-: 333 if (cnsty_chk_req_i)
-14-: 348 if (1'b1)
-15-: 351 if (otp_gnt_i)
-16-: 362 if (otp_rvalid_i)
-17-: 363 if ((otp_err inside {NoError, MacroEccCorrError}))
-18-: 366 if (1'b1)
-19-: 368 if (((digest_o == data_mux) || (digest_o == '0)))
-20-: 381 if (((scrmbl_data_o == data_mux) || lc_ctrl_pkg::lc_tx_test_true_strict(check_byp_en_i)))
-21-: 385 if ((cnt == LastScrmblBlock))
-22-: 401 if ((otp_err != NoError))
-23-: 417 if (1'b1)
-24-: 424 if (1'b0)
-25-: 426 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-26-: 433 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-27-: 444 if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-28-: 459 if (scrmbl_ready_i)
-29-: 469 if (scrmbl_valid_i)
-30-: 482 if (scrmbl_ready_i)
-31-: 485 if ((cnt == PenultimateScrmblBlock))
-32-: 489 if (cnt[0])
-33-: 498 if (cnt[0])
-34-: 503 if (1'b0)
-35-: 519 if (scrmbl_ready_i)
-36-: 531 if (scrmbl_ready_i)
-37-: 544 if (scrmbl_valid_i)
-38-: 547 if (((digest_o == data_mux) || (digest_o == '0)))
-39-: 551 if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-40-: 573 if ((error_q == NoError))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | -17- | -18- | -19- | -20- | -21- | -22- | -23- | -24- | -25- | -26- | -27- | -28- | -29- | -30- | -31- | -32- | -33- | -34- | -35- | -36- | -37- | -38- | -39- | -40- | Status | Tests |
ResetSt |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
ResetSt |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitSt |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitSt |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
1 |
1 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
InitWaitSt |
- |
- |
1 |
1 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
1 |
1 |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T11,T43,T44 |
InitWaitSt |
- |
- |
1 |
1 |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T80,T44,T81 |
InitWaitSt |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitDescrSt |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
InitDescrSt |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
InitDescrWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
InitDescrWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IdleSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
IdleSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
IdleSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
IdleSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
CnstyReadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
CnstyReadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
CnstyReadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
CnstyReadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T26 |
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T29,T30,T45 |
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T82,T83,T46 |
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
IntegDigClrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
IntegDigClrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IntegDigClrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigClrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigClrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
IntegDigClrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IntegScrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IntegScrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IntegScrWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IntegScrWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Unreachable |
|
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigPadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigPadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Not Covered |
|
IntegDigFinSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigFinSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
Covered |
T1,T2,T3 |
IntegDigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
Covered |
T2,T3,T4 |
IntegDigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
Covered |
T47,T32,T48 |
IntegDigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T20,T21,T22 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T20,T21,T22 |
LineNo. Expression
-1-: 595 if (ecc_err)
-2-: 597 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Not Covered |
|
1 |
0 |
Not Covered |
|
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 602 if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-: 605 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T1,T2,T3 |
1 |
0 |
Covered |
T1,T2,T3 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 750 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 753 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=2040,StateWidth=12 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
56 |
39 |
69.64 |
TERNARY |
636 |
2 |
1 |
50.00 |
TERNARY |
652 |
2 |
1 |
50.00 |
TERNARY |
678 |
2 |
2 |
100.00 |
CASE |
240 |
40 |
27 |
67.50 |
IF |
595 |
3 |
1 |
33.33 |
IF |
602 |
3 |
3 |
100.00 |
IF |
750 |
2 |
2 |
100.00 |
IF |
753 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 636 ((base_sel == DigOffset)) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 652 ((data_sel == ScrmblData)) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 678 (init_done_o) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 240 case (state_q)
-2-: 245 if (init_req_i)
-3-: 255 if (otp_gnt_i)
-4-: 265 if (otp_rvalid_i)
-5-: 267 if ((otp_err inside {NoError, MacroEccCorrError}))
-6-: 271 if ((cnt == LastScrmblBlock))
-7-: 275 if (1'b0)
-8-: 282 if ((otp_err != NoError))
-9-: 302 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-10-: 314 if (scrmbl_valid_i)
-11-: 324 if (integ_chk_req_i)
-12-: 325 if (1'b0)
-13-: 333 if (cnsty_chk_req_i)
-14-: 348 if (1'b0)
-15-: 351 if (otp_gnt_i)
-16-: 362 if (otp_rvalid_i)
-17-: 363 if ((otp_err inside {NoError, MacroEccCorrError}))
-18-: 366 if (1'b0)
-19-: 368 if (((digest_o == data_mux) || (digest_o == '0)))
-20-: 381 if (((scrmbl_data_o == data_mux) || lc_ctrl_pkg::lc_tx_test_true_strict(check_byp_en_i)))
-21-: 385 if ((cnt == LastScrmblBlock))
-22-: 401 if ((otp_err != NoError))
-23-: 417 if (1'b0)
-24-: 424 if (1'b0)
-25-: 426 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-26-: 433 if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-27-: 444 if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-28-: 459 if (scrmbl_ready_i)
-29-: 469 if (scrmbl_valid_i)
-30-: 482 if (scrmbl_ready_i)
-31-: 485 if ((cnt == PenultimateScrmblBlock))
-32-: 489 if (cnt[0])
-33-: 498 if (cnt[0])
-34-: 503 if (1'b0)
-35-: 519 if (scrmbl_ready_i)
-36-: 531 if (scrmbl_ready_i)
-37-: 544 if (scrmbl_valid_i)
-38-: 547 if (((digest_o == data_mux) || (digest_o == '0)))
-39-: 551 if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-40-: 573 if ((error_q == NoError))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | -17- | -18- | -19- | -20- | -21- | -22- | -23- | -24- | -25- | -26- | -27- | -28- | -29- | -30- | -31- | -32- | -33- | -34- | -35- | -36- | -37- | -38- | -39- | -40- | Status | Tests |
ResetSt |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
ResetSt |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitSt |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitSt |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
1 |
1 |
0 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
InitWaitSt |
- |
- |
1 |
1 |
0 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
1 |
1 |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T23,T58,T51 |
InitWaitSt |
- |
- |
1 |
1 |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T11,T84,T85 |
InitWaitSt |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitDescrSt |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
InitDescrSt |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
InitDescrWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
InitDescrWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IdleSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
IdleSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
IdleSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
IdleSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
CnstyReadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
CnstyReadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
CnstyReadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
CnstyReadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T58,T51,T36 |
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T59,T60 |
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T68,T78,T41 |
CnstyReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T4 |
IntegDigClrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
IntegDigClrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IntegDigClrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
IntegDigClrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IntegDigClrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IntegDigClrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IntegScrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
IntegScrSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IntegScrWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
IntegScrWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
Unreachable |
|
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IntegDigSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
IntegDigPadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
Unreachable |
|
IntegDigPadSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Not Covered |
|
IntegDigFinSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
Unreachable |
|
IntegDigFinSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
Not Covered |
|
IntegDigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
Unreachable |
|
IntegDigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
Unreachable |
|
IntegDigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
Unreachable |
|
IntegDigWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
Not Covered |
|
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T20,T21,T22 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T3 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T20,T21,T22 |
LineNo. Expression
-1-: 595 if (ecc_err)
-2-: 597 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Not Covered |
|
1 |
0 |
Not Covered |
|
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 602 if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-: 605 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T1,T2,T3 |
1 |
0 |
Covered |
T1,T2,T3 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 750 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 753 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
otp_ctrl_part_buf
Assertion Details
AccessKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
401064 |
399414 |
0 |
0 |
T2 |
81252 |
79608 |
0 |
0 |
T3 |
95358 |
93216 |
0 |
0 |
T4 |
1579992 |
1579848 |
0 |
0 |
T5 |
87972 |
86442 |
0 |
0 |
T6 |
3291792 |
3291630 |
0 |
0 |
T8 |
64026 |
63066 |
0 |
0 |
T9 |
42414 |
41916 |
0 |
0 |
T10 |
96810 |
94968 |
0 |
0 |
T11 |
91848 |
90126 |
0 |
0 |
BypassEnable0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1456570290 |
0 |
0 |
T1 |
200532 |
199707 |
0 |
0 |
T2 |
40626 |
39804 |
0 |
0 |
T3 |
47679 |
46608 |
0 |
0 |
T4 |
789996 |
789924 |
0 |
0 |
T5 |
43986 |
43221 |
0 |
0 |
T6 |
1645896 |
1645815 |
0 |
0 |
T8 |
32013 |
31533 |
0 |
0 |
T9 |
21207 |
20958 |
0 |
0 |
T10 |
48405 |
47484 |
0 |
0 |
T11 |
45924 |
45063 |
0 |
0 |
BypassEnable1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
334220 |
332845 |
0 |
0 |
T2 |
67710 |
66340 |
0 |
0 |
T3 |
79465 |
77680 |
0 |
0 |
T4 |
1316660 |
1316540 |
0 |
0 |
T5 |
73310 |
72035 |
0 |
0 |
T6 |
2743160 |
2743025 |
0 |
0 |
T8 |
53355 |
52555 |
0 |
0 |
T9 |
35345 |
34930 |
0 |
0 |
T10 |
80675 |
79140 |
0 |
0 |
T11 |
76540 |
75105 |
0 |
0 |
CnstyChkAckKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
401064 |
399414 |
0 |
0 |
T2 |
81252 |
79608 |
0 |
0 |
T3 |
95358 |
93216 |
0 |
0 |
T4 |
1579992 |
1579848 |
0 |
0 |
T5 |
87972 |
86442 |
0 |
0 |
T6 |
3291792 |
3291630 |
0 |
0 |
T8 |
64026 |
63066 |
0 |
0 |
T9 |
42414 |
41916 |
0 |
0 |
T10 |
96810 |
94968 |
0 |
0 |
T11 |
91848 |
90126 |
0 |
0 |
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
401064 |
399414 |
0 |
0 |
T2 |
81252 |
79608 |
0 |
0 |
T3 |
95358 |
93216 |
0 |
0 |
T4 |
1579992 |
1579848 |
0 |
0 |
T5 |
87972 |
86442 |
0 |
0 |
T6 |
3291792 |
3291630 |
0 |
0 |
T8 |
64026 |
63066 |
0 |
0 |
T9 |
42414 |
41916 |
0 |
0 |
T10 |
96810 |
94968 |
0 |
0 |
T11 |
91848 |
90126 |
0 |
0 |
DigestKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
401064 |
399414 |
0 |
0 |
T2 |
81252 |
79608 |
0 |
0 |
T3 |
95358 |
93216 |
0 |
0 |
T4 |
1579992 |
1579848 |
0 |
0 |
T5 |
87972 |
86442 |
0 |
0 |
T6 |
3291792 |
3291630 |
0 |
0 |
T8 |
64026 |
63066 |
0 |
0 |
T9 |
42414 |
41916 |
0 |
0 |
T10 |
96810 |
94968 |
0 |
0 |
T11 |
91848 |
90126 |
0 |
0 |
DigestOffsetMustBeRepresentable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6900 |
6900 |
0 |
0 |
T1 |
6 |
6 |
0 |
0 |
T2 |
6 |
6 |
0 |
0 |
T3 |
6 |
6 |
0 |
0 |
T4 |
6 |
6 |
0 |
0 |
T5 |
6 |
6 |
0 |
0 |
T6 |
6 |
6 |
0 |
0 |
T8 |
6 |
6 |
0 |
0 |
T9 |
6 |
6 |
0 |
0 |
T10 |
6 |
6 |
0 |
0 |
T11 |
6 |
6 |
0 |
0 |
EccErrorState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
ErrorKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
401064 |
399414 |
0 |
0 |
T2 |
81252 |
79608 |
0 |
0 |
T3 |
95358 |
93216 |
0 |
0 |
T4 |
1579992 |
1579848 |
0 |
0 |
T5 |
87972 |
86442 |
0 |
0 |
T6 |
3291792 |
3291630 |
0 |
0 |
T8 |
64026 |
63066 |
0 |
0 |
T9 |
42414 |
41916 |
0 |
0 |
T10 |
96810 |
94968 |
0 |
0 |
T11 |
91848 |
90126 |
0 |
0 |
InitDoneKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
401064 |
399414 |
0 |
0 |
T2 |
81252 |
79608 |
0 |
0 |
T3 |
95358 |
93216 |
0 |
0 |
T4 |
1579992 |
1579848 |
0 |
0 |
T5 |
87972 |
86442 |
0 |
0 |
T6 |
3291792 |
3291630 |
0 |
0 |
T8 |
64026 |
63066 |
0 |
0 |
T9 |
42414 |
41916 |
0 |
0 |
T10 |
96810 |
94968 |
0 |
0 |
T11 |
91848 |
90126 |
0 |
0 |
InitReadLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
759036990 |
0 |
0 |
T1 |
401064 |
347354 |
0 |
0 |
T2 |
81252 |
50742 |
0 |
0 |
T3 |
95358 |
35838 |
0 |
0 |
T4 |
1579992 |
2930907 |
0 |
0 |
T5 |
87972 |
38591 |
0 |
0 |
T6 |
3291792 |
5052476 |
0 |
0 |
T8 |
64026 |
24432 |
0 |
0 |
T9 |
42414 |
7848 |
0 |
0 |
T10 |
96810 |
42014 |
0 |
0 |
T11 |
91848 |
45384 |
0 |
0 |
InitWriteLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
759036990 |
0 |
0 |
T1 |
401064 |
347354 |
0 |
0 |
T2 |
81252 |
50742 |
0 |
0 |
T3 |
95358 |
35838 |
0 |
0 |
T4 |
1579992 |
2930907 |
0 |
0 |
T5 |
87972 |
38591 |
0 |
0 |
T6 |
3291792 |
5052476 |
0 |
0 |
T8 |
64026 |
24432 |
0 |
0 |
T9 |
42414 |
7848 |
0 |
0 |
T10 |
96810 |
42014 |
0 |
0 |
T11 |
91848 |
45384 |
0 |
0 |
IntegChkAckKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
401064 |
399414 |
0 |
0 |
T2 |
81252 |
79608 |
0 |
0 |
T3 |
95358 |
93216 |
0 |
0 |
T4 |
1579992 |
1579848 |
0 |
0 |
T5 |
87972 |
86442 |
0 |
0 |
T6 |
3291792 |
3291630 |
0 |
0 |
T8 |
64026 |
63066 |
0 |
0 |
T9 |
42414 |
41916 |
0 |
0 |
T10 |
96810 |
94968 |
0 |
0 |
T11 |
91848 |
90126 |
0 |
0 |
OffsetMustBeBlockAligned_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6900 |
6900 |
0 |
0 |
T1 |
6 |
6 |
0 |
0 |
T2 |
6 |
6 |
0 |
0 |
T3 |
6 |
6 |
0 |
0 |
T4 |
6 |
6 |
0 |
0 |
T5 |
6 |
6 |
0 |
0 |
T6 |
6 |
6 |
0 |
0 |
T8 |
6 |
6 |
0 |
0 |
T9 |
6 |
6 |
0 |
0 |
T10 |
6 |
6 |
0 |
0 |
T11 |
6 |
6 |
0 |
0 |
OtpAddrKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
401064 |
399414 |
0 |
0 |
T2 |
81252 |
79608 |
0 |
0 |
T3 |
95358 |
93216 |
0 |
0 |
T4 |
1579992 |
1579848 |
0 |
0 |
T5 |
87972 |
86442 |
0 |
0 |
T6 |
3291792 |
3291630 |
0 |
0 |
T8 |
64026 |
63066 |
0 |
0 |
T9 |
42414 |
41916 |
0 |
0 |
T10 |
96810 |
94968 |
0 |
0 |
T11 |
91848 |
90126 |
0 |
0 |
OtpCmdKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
401064 |
399414 |
0 |
0 |
T2 |
81252 |
79608 |
0 |
0 |
T3 |
95358 |
93216 |
0 |
0 |
T4 |
1579992 |
1579848 |
0 |
0 |
T5 |
87972 |
86442 |
0 |
0 |
T6 |
3291792 |
3291630 |
0 |
0 |
T8 |
64026 |
63066 |
0 |
0 |
T9 |
42414 |
41916 |
0 |
0 |
T10 |
96810 |
94968 |
0 |
0 |
T11 |
91848 |
90126 |
0 |
0 |
OtpErrorState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
486419960 |
12 |
0 |
0 |
T7 |
104678 |
0 |
0 |
0 |
T11 |
15308 |
1 |
0 |
0 |
T12 |
697802 |
0 |
0 |
0 |
T13 |
47098 |
0 |
0 |
0 |
T27 |
96461 |
0 |
0 |
0 |
T35 |
34966 |
0 |
0 |
0 |
T41 |
0 |
1 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
T55 |
14322 |
0 |
0 |
0 |
T56 |
14233 |
0 |
0 |
0 |
T60 |
0 |
1 |
0 |
0 |
T68 |
0 |
1 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T84 |
0 |
1 |
0 |
0 |
T85 |
0 |
1 |
0 |
0 |
T86 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
33600 |
0 |
0 |
0 |
T89 |
3395 |
0 |
0 |
0 |
OtpPartBufSize_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6900 |
6900 |
0 |
0 |
T1 |
6 |
6 |
0 |
0 |
T2 |
6 |
6 |
0 |
0 |
T3 |
6 |
6 |
0 |
0 |
T4 |
6 |
6 |
0 |
0 |
T5 |
6 |
6 |
0 |
0 |
T6 |
6 |
6 |
0 |
0 |
T8 |
6 |
6 |
0 |
0 |
T9 |
6 |
6 |
0 |
0 |
T10 |
6 |
6 |
0 |
0 |
T11 |
6 |
6 |
0 |
0 |
OtpReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
401064 |
399414 |
0 |
0 |
T2 |
81252 |
79608 |
0 |
0 |
T3 |
95358 |
93216 |
0 |
0 |
T4 |
1579992 |
1579848 |
0 |
0 |
T5 |
87972 |
86442 |
0 |
0 |
T6 |
3291792 |
3291630 |
0 |
0 |
T8 |
64026 |
63066 |
0 |
0 |
T9 |
42414 |
41916 |
0 |
0 |
T10 |
96810 |
94968 |
0 |
0 |
T11 |
91848 |
90126 |
0 |
0 |
OtpSizeKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
401064 |
399414 |
0 |
0 |
T2 |
81252 |
79608 |
0 |
0 |
T3 |
95358 |
93216 |
0 |
0 |
T4 |
1579992 |
1579848 |
0 |
0 |
T5 |
87972 |
86442 |
0 |
0 |
T6 |
3291792 |
3291630 |
0 |
0 |
T8 |
64026 |
63066 |
0 |
0 |
T9 |
42414 |
41916 |
0 |
0 |
T10 |
96810 |
94968 |
0 |
0 |
T11 |
91848 |
90126 |
0 |
0 |
OtpWdataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
401064 |
399414 |
0 |
0 |
T2 |
81252 |
79608 |
0 |
0 |
T3 |
95358 |
93216 |
0 |
0 |
T4 |
1579992 |
1579848 |
0 |
0 |
T5 |
87972 |
86442 |
0 |
0 |
T6 |
3291792 |
3291630 |
0 |
0 |
T8 |
64026 |
63066 |
0 |
0 |
T9 |
42414 |
41916 |
0 |
0 |
T10 |
96810 |
94968 |
0 |
0 |
T11 |
91848 |
90126 |
0 |
0 |
ReadLockImpliesDigest_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
334220 |
332845 |
0 |
0 |
T2 |
67710 |
66340 |
0 |
0 |
T3 |
79465 |
77680 |
0 |
0 |
T4 |
1316660 |
1316540 |
0 |
0 |
T5 |
73310 |
72035 |
0 |
0 |
T6 |
2743160 |
2743025 |
0 |
0 |
T8 |
53355 |
52555 |
0 |
0 |
T9 |
35345 |
34930 |
0 |
0 |
T10 |
80675 |
79140 |
0 |
0 |
T11 |
76540 |
75105 |
0 |
0 |
ReadLockPropagation_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
752263285 |
0 |
0 |
T1 |
66844 |
66569 |
0 |
0 |
T2 |
13542 |
13268 |
0 |
0 |
T3 |
15893 |
15536 |
0 |
0 |
T4 |
263332 |
263308 |
0 |
0 |
T5 |
14662 |
14407 |
0 |
0 |
T6 |
548632 |
548605 |
0 |
0 |
T7 |
209356 |
46161 |
0 |
0 |
T8 |
10671 |
10511 |
0 |
0 |
T9 |
7069 |
6986 |
0 |
0 |
T10 |
16135 |
15828 |
0 |
0 |
T11 |
15308 |
15021 |
0 |
0 |
T12 |
1395604 |
0 |
0 |
0 |
T13 |
47098 |
0 |
0 |
0 |
T27 |
96461 |
11275 |
0 |
0 |
T28 |
0 |
3107 |
0 |
0 |
T55 |
28644 |
0 |
0 |
0 |
T56 |
28466 |
0 |
0 |
0 |
T64 |
31668 |
0 |
0 |
0 |
T73 |
0 |
143015 |
0 |
0 |
T88 |
67200 |
0 |
0 |
0 |
T89 |
6790 |
0 |
0 |
0 |
T90 |
0 |
17313 |
0 |
0 |
T91 |
0 |
40527 |
0 |
0 |
T92 |
0 |
40184 |
0 |
0 |
T93 |
0 |
2166 |
0 |
0 |
T94 |
0 |
540 |
0 |
0 |
T95 |
0 |
47732 |
0 |
0 |
T96 |
0 |
4628 |
0 |
0 |
T97 |
79864 |
0 |
0 |
0 |
T98 |
5495 |
0 |
0 |
0 |
ScrambledImpliesDigest_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1456570290 |
0 |
0 |
T1 |
200532 |
199707 |
0 |
0 |
T2 |
40626 |
39804 |
0 |
0 |
T3 |
47679 |
46608 |
0 |
0 |
T4 |
789996 |
789924 |
0 |
0 |
T5 |
43986 |
43221 |
0 |
0 |
T6 |
1645896 |
1645815 |
0 |
0 |
T8 |
32013 |
31533 |
0 |
0 |
T9 |
21207 |
20958 |
0 |
0 |
T10 |
48405 |
47484 |
0 |
0 |
T11 |
45924 |
45063 |
0 |
0 |
ScrmblCmdKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
401064 |
399414 |
0 |
0 |
T2 |
81252 |
79608 |
0 |
0 |
T3 |
95358 |
93216 |
0 |
0 |
T4 |
1579992 |
1579848 |
0 |
0 |
T5 |
87972 |
86442 |
0 |
0 |
T6 |
3291792 |
3291630 |
0 |
0 |
T8 |
64026 |
63066 |
0 |
0 |
T9 |
42414 |
41916 |
0 |
0 |
T10 |
96810 |
94968 |
0 |
0 |
T11 |
91848 |
90126 |
0 |
0 |
ScrmblDataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
401064 |
399414 |
0 |
0 |
T2 |
81252 |
79608 |
0 |
0 |
T3 |
95358 |
93216 |
0 |
0 |
T4 |
1579992 |
1579848 |
0 |
0 |
T5 |
87972 |
86442 |
0 |
0 |
T6 |
3291792 |
3291630 |
0 |
0 |
T8 |
64026 |
63066 |
0 |
0 |
T9 |
42414 |
41916 |
0 |
0 |
T10 |
96810 |
94968 |
0 |
0 |
T11 |
91848 |
90126 |
0 |
0 |
ScrmblModeKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
401064 |
399414 |
0 |
0 |
T2 |
81252 |
79608 |
0 |
0 |
T3 |
95358 |
93216 |
0 |
0 |
T4 |
1579992 |
1579848 |
0 |
0 |
T5 |
87972 |
86442 |
0 |
0 |
T6 |
3291792 |
3291630 |
0 |
0 |
T8 |
64026 |
63066 |
0 |
0 |
T9 |
42414 |
41916 |
0 |
0 |
T10 |
96810 |
94968 |
0 |
0 |
T11 |
91848 |
90126 |
0 |
0 |
ScrmblMtxReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
401064 |
399414 |
0 |
0 |
T2 |
81252 |
79608 |
0 |
0 |
T3 |
95358 |
93216 |
0 |
0 |
T4 |
1579992 |
1579848 |
0 |
0 |
T5 |
87972 |
86442 |
0 |
0 |
T6 |
3291792 |
3291630 |
0 |
0 |
T8 |
64026 |
63066 |
0 |
0 |
T9 |
42414 |
41916 |
0 |
0 |
T10 |
96810 |
94968 |
0 |
0 |
T11 |
91848 |
90126 |
0 |
0 |
ScrmblSelKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
401064 |
399414 |
0 |
0 |
T2 |
81252 |
79608 |
0 |
0 |
T3 |
95358 |
93216 |
0 |
0 |
T4 |
1579992 |
1579848 |
0 |
0 |
T5 |
87972 |
86442 |
0 |
0 |
T6 |
3291792 |
3291630 |
0 |
0 |
T8 |
64026 |
63066 |
0 |
0 |
T9 |
42414 |
41916 |
0 |
0 |
T10 |
96810 |
94968 |
0 |
0 |
T11 |
91848 |
90126 |
0 |
0 |
ScrmblValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
401064 |
399414 |
0 |
0 |
T2 |
81252 |
79608 |
0 |
0 |
T3 |
95358 |
93216 |
0 |
0 |
T4 |
1579992 |
1579848 |
0 |
0 |
T5 |
87972 |
86442 |
0 |
0 |
T6 |
3291792 |
3291630 |
0 |
0 |
T8 |
64026 |
63066 |
0 |
0 |
T9 |
42414 |
41916 |
0 |
0 |
T10 |
96810 |
94968 |
0 |
0 |
T11 |
91848 |
90126 |
0 |
0 |
SizeMustBeBlockAligned_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6900 |
6900 |
0 |
0 |
T1 |
6 |
6 |
0 |
0 |
T2 |
6 |
6 |
0 |
0 |
T3 |
6 |
6 |
0 |
0 |
T4 |
6 |
6 |
0 |
0 |
T5 |
6 |
6 |
0 |
0 |
T6 |
6 |
6 |
0 |
0 |
T8 |
6 |
6 |
0 |
0 |
T9 |
6 |
6 |
0 |
0 |
T10 |
6 |
6 |
0 |
0 |
T11 |
6 |
6 |
0 |
0 |
WriteLockImpliesDigest_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1456570290 |
0 |
0 |
T1 |
200532 |
199707 |
0 |
0 |
T2 |
40626 |
39804 |
0 |
0 |
T3 |
47679 |
46608 |
0 |
0 |
T4 |
789996 |
789924 |
0 |
0 |
T5 |
43986 |
43221 |
0 |
0 |
T6 |
1645896 |
1645815 |
0 |
0 |
T8 |
32013 |
31533 |
0 |
0 |
T9 |
21207 |
20958 |
0 |
0 |
T10 |
48405 |
47484 |
0 |
0 |
T11 |
45924 |
45063 |
0 |
0 |
WriteLockPropagation_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
756122209 |
0 |
0 |
T1 |
66844 |
66569 |
0 |
0 |
T2 |
13542 |
13268 |
0 |
0 |
T3 |
15893 |
15536 |
0 |
0 |
T4 |
263332 |
263308 |
0 |
0 |
T5 |
14662 |
14407 |
0 |
0 |
T6 |
548632 |
548605 |
0 |
0 |
T7 |
209356 |
94625 |
0 |
0 |
T8 |
10671 |
10511 |
0 |
0 |
T9 |
7069 |
6986 |
0 |
0 |
T10 |
16135 |
15828 |
0 |
0 |
T11 |
15308 |
15021 |
0 |
0 |
T12 |
1395604 |
0 |
0 |
0 |
T27 |
96461 |
4130 |
0 |
0 |
T28 |
0 |
6398 |
0 |
0 |
T43 |
10730 |
0 |
0 |
0 |
T55 |
28644 |
0 |
0 |
0 |
T56 |
28466 |
0 |
0 |
0 |
T64 |
31668 |
0 |
0 |
0 |
T73 |
0 |
99418 |
0 |
0 |
T88 |
67200 |
0 |
0 |
0 |
T89 |
6790 |
0 |
0 |
0 |
T91 |
0 |
43721 |
0 |
0 |
T94 |
0 |
3031 |
0 |
0 |
T95 |
0 |
15997 |
0 |
0 |
T96 |
0 |
7487 |
0 |
0 |
T97 |
79864 |
0 |
0 |
0 |
T98 |
5495 |
0 |
0 |
0 |
T99 |
0 |
5122 |
0 |
0 |
T100 |
0 |
21103 |
0 |
0 |
T101 |
0 |
1516 |
0 |
0 |
gen_digest_read_lock.DigestReadLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1459259880 |
58329450 |
0 |
0 |
T7 |
314034 |
882130 |
0 |
0 |
T12 |
2093406 |
0 |
0 |
0 |
T13 |
141294 |
24020 |
0 |
0 |
T27 |
289383 |
110261 |
0 |
0 |
T28 |
0 |
70909 |
0 |
0 |
T35 |
34966 |
4006 |
0 |
0 |
T55 |
42966 |
2660 |
0 |
0 |
T56 |
42699 |
3546 |
0 |
0 |
T62 |
0 |
2624 |
0 |
0 |
T64 |
31668 |
0 |
0 |
0 |
T73 |
0 |
1419911 |
0 |
0 |
T88 |
100800 |
0 |
0 |
0 |
T89 |
10185 |
0 |
0 |
0 |
T90 |
0 |
108481 |
0 |
0 |
T91 |
0 |
479354 |
0 |
0 |
T92 |
0 |
190367 |
0 |
0 |
T93 |
0 |
14585 |
0 |
0 |
T94 |
0 |
19639 |
0 |
0 |
T95 |
0 |
80202 |
0 |
0 |
T96 |
0 |
45747 |
0 |
0 |
T97 |
119796 |
2002 |
0 |
0 |
T102 |
0 |
1331 |
0 |
0 |
gen_digest_write_lock.DigestWriteLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
105501171 |
0 |
0 |
T3 |
15893 |
5397 |
0 |
0 |
T4 |
263332 |
0 |
0 |
0 |
T5 |
14662 |
0 |
0 |
0 |
T6 |
548632 |
0 |
0 |
0 |
T7 |
418712 |
1635680 |
0 |
0 |
T8 |
10671 |
0 |
0 |
0 |
T9 |
7069 |
0 |
0 |
0 |
T10 |
16135 |
0 |
0 |
0 |
T11 |
15308 |
0 |
0 |
0 |
T12 |
2791208 |
0 |
0 |
0 |
T13 |
188392 |
73029 |
0 |
0 |
T27 |
482305 |
254588 |
0 |
0 |
T28 |
0 |
132362 |
0 |
0 |
T35 |
104898 |
46497 |
0 |
0 |
T55 |
57288 |
8303 |
0 |
0 |
T56 |
56932 |
10961 |
0 |
0 |
T62 |
0 |
2624 |
0 |
0 |
T64 |
31668 |
0 |
0 |
0 |
T73 |
0 |
2031102 |
0 |
0 |
T88 |
134400 |
0 |
0 |
0 |
T89 |
13580 |
0 |
0 |
0 |
T90 |
0 |
197891 |
0 |
0 |
T91 |
0 |
479354 |
0 |
0 |
T92 |
0 |
190367 |
0 |
0 |
T93 |
0 |
14585 |
0 |
0 |
T94 |
0 |
19639 |
0 |
0 |
T95 |
0 |
80202 |
0 |
0 |
T96 |
0 |
45747 |
0 |
0 |
T97 |
159728 |
6329 |
0 |
0 |
T102 |
0 |
1331 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
401064 |
399414 |
0 |
0 |
T2 |
81252 |
79608 |
0 |
0 |
T3 |
95358 |
93216 |
0 |
0 |
T4 |
1579992 |
1579848 |
0 |
0 |
T5 |
87972 |
86442 |
0 |
0 |
T6 |
3291792 |
3291630 |
0 |
0 |
T8 |
64026 |
63066 |
0 |
0 |
T9 |
42414 |
41916 |
0 |
0 |
T10 |
96810 |
94968 |
0 |
0 |
T11 |
91848 |
90126 |
0 |
0 |