Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.94		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.94		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.17	94.16	96.15	96.94		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T5,T4,T8
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T72,T153,T154
1	Covered	T72,T153,T154

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T4,T8

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T4,T8

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T5,T4,T8
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T5,T4,T8
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T35

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T35

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T3,T5,T4
ReadWaitSt	252	Covered	T5,T4,T8
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T3,T5,T4
InitSt->ErrorSt	315	Covered	T190,T191
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T97,T102,T192
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T4,T6
ReadSt->ReadWaitSt	252	Covered	T5,T4,T8
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T5,T4,T8
ResetSt->ErrorSt	315	Covered	T72,T73,T74
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T3,T4,T6
CheckFailError	317	Covered	T72,T153,T154
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T4,T6,T7
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T3,T4,T6
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T72,T153,T154
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T3,T4,T6
NoError->CheckFailError	317	Covered	T72,T153,T154
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T4,T8

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T4,T8

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T35
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T5,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T5,T4,T8
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T35,T7,T28
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T4,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T5,T4,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T5,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T72,T153,T154
1	0	Covered	T72,T153,T154
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	486419960	485523430	0	0
DigestKnown_A	486419960	485523430	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	486419960	18045	0	0
ErrorKnown_A	486419960	485523430	0	0
FsmStateKnown_A	486419960	485523430	0	0
InitDoneKnown_A	486419960	485523430	0	0
InitReadLocksPartition_A	486419960	114453727	0	0
InitWriteLocksPartition_A	486419960	114453727	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	486419960	485523430	0	0
OtpCmdKnown_A	486419960	485523430	0	0
OtpErrorState_A	486419960	0	0	0
OtpReqKnown_A	486419960	485523430	0	0
OtpSizeKnown_A	486419960	485523430	0	0
OtpWdataKnown_A	486419960	485523430	0	0
ReadLockPropagation_A	486419960	206169490	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	486419960	485523430	0	0
TlulRdataKnown_A	486419960	485523430	0	0
TlulReadOnReadLock_A	486419960	8057	0	0
TlulRerrorKnown_A	486419960	485523430	0	0
TlulRvalidKnown_A	486419960	485523430	0	0
WriteLockPropagation_A	486419960	1964050	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	486419960	25930856	0	0
u_state_regs_A	486419960	485523430	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	18045	0	0
T14	129868	0	0	0
T28	55709	0	0	0
T72	14442	2502	0	0
T73	123292	0	0	0
T90	71223	0	0	0
T91	392512	0	0	0
T102	44272	0	0	0
T150	21584	0	0	0
T153	0	3728	0	0
T154	0	3010	0	0
T158	0	2205	0	0
T159	11629	0	0	0
T161	0	3651	0	0
T162	0	2949	0	0
T163	11998	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	114453727	0	0
T1	66844	55167	0	0
T2	13542	6050	0	0
T3	15893	1386	0	0
T4	263332	478926	0	0
T5	14662	4081	0	0
T6	548632	983028	0	0
T8	10671	2844	0	0
T9	7069	104	0	0
T10	16135	4631	0	0
T11	15308	5981	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	114453727	0	0
T1	66844	55167	0	0
T2	13542	6050	0	0
T3	15893	1386	0	0
T4	263332	478926	0	0
T5	14662	4081	0	0
T6	548632	983028	0	0
T8	10671	2844	0	0
T9	7069	104	0	0
T10	16135	4631	0	0
T11	15308	5981	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	206169490	0	0
T3	15893	454	0	0
T4	263332	345137	0	0
T5	14662	0	0	0
T6	548632	164343	0	0
T7	0	267111	0	0
T8	10671	0	0	0
T9	7069	0	0	0
T10	16135	0	0	0
T11	15308	0	0	0
T12	0	403509	0	0
T13	0	25024	0	0
T27	96461	5671	0	0
T35	34966	4840	0	0
T90	0	6527	0	0
T97	0	4303	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	8057	0	0
T1	66844	6	0	0
T2	13542	3	0	0
T3	15893	1	0	0
T4	263332	15	0	0
T5	14662	0	0	0
T6	548632	19	0	0
T7	0	57	0	0
T8	10671	0	0	0
T9	7069	0	0	0
T10	16135	0	0	0
T11	15308	0	0	0
T13	0	6	0	0
T27	0	6	0	0
T35	0	8	0	0
T88	0	8	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	1964050	0	0
T7	104678	41162	0	0
T12	697802	0	0	0
T28	0	3638	0	0
T43	10730	0	0	0
T55	14322	0	0	0
T56	14233	0	0	0
T64	15834	0	0	0
T73	0	60395	0	0
T88	33600	0	0	0
T89	3395	0	0	0
T91	0	17277	0	0
T92	0	17375	0	0
T94	0	173	0	0
T96	0	4839	0	0
T97	39932	0	0	0
T98	5495	0	0	0
T99	0	6466	0	0
T100	0	19933	0	0
T117	0	22086	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	25930856	0	0
T6	548632	0	0	0
T7	104678	421347	0	0
T10	16135	3550	0	0
T11	15308	4208	0	0
T13	47098	25754	0	0
T27	96461	78592	0	0
T28	0	36681	0	0
T35	34966	24161	0	0
T43	0	3361	0	0
T55	14322	0	0	0
T56	14233	0	0	0
T73	0	734049	0	0
T88	33600	0	0	0
T90	0	59826	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T104,T155,T156

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T5,T4,T8
1	Covered	T27,T62,T157

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T72,T153,T158
1	Covered	T72,T153,T158

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T4,T8

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T4,T8

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T5,T4,T8
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T5,T4,T8
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T35,T27

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T35,T27

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T5,T4,T8
ReadWaitSt	252	Covered	T5,T4,T8
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T5,T4,T8
InitSt->ErrorSt	315	Covered	T97,T102,T190
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T177,T178,T179
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T6,T35
ReadSt->ReadWaitSt	252	Covered	T5,T4,T8
ReadWaitSt->ErrorSt	276	Covered	T146,T183,T147
ReadWaitSt->IdleSt	270	Covered	T5,T4,T8
ResetSt->ErrorSt	315	Covered	T72,T73,T74
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T4,T6,T35
CheckFailError	317	Covered	T72,T153,T158
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T27,T104,T62
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T4,T7,T14
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T6,T35,T27
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T72,T153,T158
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T104,T157,T155
MacroEccCorrError->NoError	235	Covered	T27,T62,T193
NoError->AccessError	256	Covered	T4,T6,T35
NoError->CheckFailError	317	Covered	T72,T153,T158
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Covered	T27,T104,T62

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T4,T8

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T4,T8

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T35,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T104,T155,T156
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T177,T178,T179
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T4,T8
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T5,T4,T8
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T35,T7,T28
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T6,T35
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T27,T62,T157
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T5,T4,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T146,T183,T147
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T5,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T72,T153,T158
1	0	Covered	T72,T153,T158
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	486419960	485523430	0	0
DigestKnown_A	486419960	485523430	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	486419960	8435	0	0
ErrorKnown_A	486419960	485523430	0	0
FsmStateKnown_A	486419960	485523430	0	0
InitDoneKnown_A	486419960	485523430	0	0
InitReadLocksPartition_A	486419960	114643776	0	0
InitWriteLocksPartition_A	486419960	114643776	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	486419960	485523430	0	0
OtpCmdKnown_A	486419960	485523430	0	0
OtpErrorState_A	486419960	70	0	0
OtpReqKnown_A	486419960	485523430	0	0
OtpSizeKnown_A	486419960	485523430	0	0
OtpWdataKnown_A	486419960	485523430	0	0
ReadLockPropagation_A	486419960	210052377	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	486419960	485523430	0	0
TlulRdataKnown_A	486419960	485523430	0	0
TlulReadOnReadLock_A	486419960	8615	0	0
TlulRerrorKnown_A	486419960	485523430	0	0
TlulRvalidKnown_A	486419960	485523430	0	0
WriteLockPropagation_A	486419960	1902410	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	486419960	25751277	0	0
u_state_regs_A	486419960	485523430	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	8435	0	0
T14	129868	0	0	0
T28	55709	0	0	0
T72	14442	2502	0	0
T73	123292	0	0	0
T90	71223	0	0	0
T91	392512	0	0	0
T102	44272	0	0	0
T150	21584	0	0	0
T153	0	3728	0	0
T158	0	2205	0	0
T159	11629	0	0	0
T163	11998	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	114643776	0	0
T1	66844	55218	0	0
T2	13542	6084	0	0
T3	15893	1488	0	0
T4	263332	479062	0	0
T5	14662	4132	0	0
T6	548632	983164	0	0
T8	10671	2878	0	0
T9	7069	121	0	0
T10	16135	4682	0	0
T11	15308	6015	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	114643776	0	0
T1	66844	55218	0	0
T2	13542	6084	0	0
T3	15893	1488	0	0
T4	263332	479062	0	0
T5	14662	4132	0	0
T6	548632	983164	0	0
T8	10671	2878	0	0
T9	7069	121	0	0
T10	16135	4682	0	0
T11	15308	6015	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	70	0	0
T15	860547	0	0	0
T62	42684	0	0	0
T99	70138	0	0	0
T100	571847	0	0	0
T101	45358	0	0	0
T132	17352	0	0	0
T144	14476	0	0	0
T146	0	1	0	0
T171	0	1	0	0
T177	14368	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	59306	0	0	0
T187	16776	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	210052377	0	0
T1	66844	54307	0	0
T2	13542	0	0	0
T3	15893	0	0	0
T4	263332	327834	0	0
T5	14662	0	0	0
T6	548632	148264	0	0
T7	0	230156	0	0
T8	10671	0	0	0
T9	7069	0	0	0
T10	16135	0	0	0
T11	15308	0	0	0
T12	0	403503	0	0
T13	0	24989	0	0
T27	0	10837	0	0
T35	0	3058	0	0
T90	0	6725	0	0
T97	0	4936	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	8615	0	0
T1	66844	7	0	0
T2	13542	4	0	0
T3	15893	1	0	0
T4	263332	19	0	0
T5	14662	0	0	0
T6	548632	15	0	0
T7	0	68	0	0
T8	10671	0	0	0
T9	7069	0	0	0
T10	16135	0	0	0
T11	15308	0	0	0
T13	0	5	0	0
T27	0	3	0	0
T35	0	4	0	0
T88	0	13	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	1902410	0	0
T7	104678	38303	0	0
T12	697802	0	0	0
T13	47098	0	0	0
T27	96461	7049	0	0
T28	0	3274	0	0
T55	14322	0	0	0
T56	14233	0	0	0
T64	15834	0	0	0
T73	0	83582	0	0
T88	33600	0	0	0
T89	3395	0	0	0
T90	0	8755	0	0
T91	0	6815	0	0
T92	0	19047	0	0
T95	0	7789	0	0
T96	0	1001	0	0
T97	39932	0	0	0
T100	0	12151	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	25751277	0	0
T3	15893	5771	0	0
T4	263332	0	0	0
T5	14662	0	0	0
T6	548632	0	0	0
T7	0	370537	0	0
T8	10671	0	0	0
T9	7069	0	0	0
T10	16135	0	0	0
T11	15308	0	0	0
T13	0	25703	0	0
T27	96461	78320	0	0
T28	0	45133	0	0
T35	34966	24042	0	0
T73	0	679758	0	0
T90	0	59690	0	0
T91	0	222609	0	0
T102	0	2685	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T76,T84,T80

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T5,T4,T8
1	Covered	T62,T152,T157

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T72,T74,T142
1	Covered	T72,T74,T142

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T4,T8

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T5,T4,T8

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T5

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T5,T4,T8
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T5,T4,T8
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T35

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T35

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T5,T4,T8
ReadWaitSt	252	Covered	T5,T4,T8
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T5,T4,T8
InitSt->ErrorSt	315	Covered	T97,T102,T194
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T8,T10,T159
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T6,T35,T27
ReadSt->ReadWaitSt	252	Covered	T5,T4,T8
ReadWaitSt->ErrorSt	276	Covered	T146,T157,T195
ReadWaitSt->IdleSt	270	Covered	T5,T4,T8
ResetSt->ErrorSt	315	Covered	T72,T73,T74
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T6,T35,T27
CheckFailError	317	Covered	T72,T74,T142
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T62,T152,T157
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T6,T7,T14
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T6,T35,T27
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T72,T74,T142
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T152,T157,T76
MacroEccCorrError->NoError	235	Covered	T62,T103,T196
NoError->AccessError	256	Covered	T6,T35,T27
NoError->CheckFailError	317	Covered	T72,T74,T142
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Covered	T62,T152,T157

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T4,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T4,T8

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T4,T8

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T35
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T76,T84,T80
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T8,T10,T159
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T5,T4,T8
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T5,T4,T8
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T35,T7,T12
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T6,T35,T27
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T62,T152,T157
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T5,T4,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T146,T157,T195
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T5,T4,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T72,T74,T142
1	0	Covered	T72,T74,T142
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	486419960	485523430	0	0
DigestKnown_A	486419960	485523430	0	0
DigestOffsetMustBeRepresentable_A	1150	1150	0	0
EccErrorState_A	486419960	16516	0	0
ErrorKnown_A	486419960	485523430	0	0
FsmStateKnown_A	486419960	485523430	0	0
InitDoneKnown_A	486419960	485523430	0	0
InitReadLocksPartition_A	486419960	114832603	0	0
InitWriteLocksPartition_A	486419960	114832603	0	0
OffsetMustBeBlockAligned_A	1150	1150	0	0
OtpAddrKnown_A	486419960	485523430	0	0
OtpCmdKnown_A	486419960	485523430	0	0
OtpErrorState_A	486419960	65	0	0
OtpReqKnown_A	486419960	485523430	0	0
OtpSizeKnown_A	486419960	485523430	0	0
OtpWdataKnown_A	486419960	485523430	0	0
ReadLockPropagation_A	486419960	207314477	0	0
SizeMustBeBlockAligned_A	1150	1150	0	0
TlulGntKnown_A	486419960	485523430	0	0
TlulRdataKnown_A	486419960	485523430	0	0
TlulReadOnReadLock_A	486419960	8701	0	0
TlulRerrorKnown_A	486419960	485523430	0	0
TlulRvalidKnown_A	486419960	485523430	0	0
WriteLockPropagation_A	486419960	1073147	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	486419960	16172074	0	0
u_state_regs_A	486419960	485523430	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	16516	0	0
T14	129868	0	0	0
T28	55709	0	0	0
T72	14442	2502	0	0
T73	123292	0	0	0
T74	0	2196	0	0
T90	71223	0	0	0
T91	392512	0	0	0
T102	44272	0	0	0
T142	0	2936	0	0
T150	21584	0	0	0
T153	0	3728	0	0
T158	0	2205	0	0
T159	11629	0	0	0
T162	0	2949	0	0
T163	11998	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	114832603	0	0
T1	66844	55269	0	0
T2	13542	6118	0	0
T3	15893	1590	0	0
T4	263332	479198	0	0
T5	14662	4183	0	0
T6	548632	983300	0	0
T8	10671	2902	0	0
T9	7069	138	0	0
T10	16135	4723	0	0
T11	15308	6049	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	114832603	0	0
T1	66844	55269	0	0
T2	13542	6118	0	0
T3	15893	1590	0	0
T4	263332	479198	0	0
T5	14662	4183	0	0
T6	548632	983300	0	0
T8	10671	2902	0	0
T9	7069	138	0	0
T10	16135	4723	0	0
T11	15308	6049	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	65	0	0
T6	548632	0	0	0
T7	104678	0	0	0
T8	10671	1	0	0
T10	16135	1	0	0
T11	15308	0	0	0
T13	47098	0	0	0
T27	96461	0	0	0
T35	34966	0	0	0
T55	14322	0	0	0
T56	14233	0	0	0
T146	0	3	0	0
T155	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T163	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	207314477	0	0
T3	15893	452	0	0
T4	263332	322655	0	0
T5	14662	0	0	0
T6	548632	796203	0	0
T7	0	216437	0	0
T8	10671	0	0	0
T9	7069	0	0	0
T10	16135	0	0	0
T11	15308	0	0	0
T12	0	402337	0	0
T13	0	24961	0	0
T27	96461	8327	0	0
T35	34966	4832	0	0
T90	0	5934	0	0
T97	0	4292	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1150	1150	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	8701	0	0
T1	66844	4	0	0
T2	13542	1	0	0
T3	15893	0	0	0
T4	263332	13	0	0
T5	14662	0	0	0
T6	548632	20	0	0
T7	0	70	0	0
T8	10671	0	0	0
T9	7069	0	0	0
T10	16135	0	0	0
T11	15308	0	0	0
T12	0	38	0	0
T13	0	1	0	0
T27	0	3	0	0
T35	0	4	0	0
T88	0	11	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	1073147	0	0
T7	104678	20948	0	0
T12	697802	0	0	0
T43	10730	0	0	0
T55	14322	0	0	0
T56	14233	0	0	0
T64	15834	0	0	0
T73	0	88837	0	0
T88	33600	0	0	0
T89	3395	0	0	0
T91	0	2969	0	0
T94	0	1758	0	0
T95	0	25706	0	0
T96	0	1988	0	0
T97	39932	0	0	0
T98	5495	0	0	0
T99	0	10993	0	0
T100	0	8203	0	0
T117	0	2854	0	0
T189	0	2994	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	16172074	0	0
T3	15893	5737	0	0
T4	263332	0	0	0
T5	14662	0	0	0
T6	548632	0	0	0
T7	0	300328	0	0
T8	10671	0	0	0
T9	7069	0	0	0
T10	16135	3528	0	0
T11	15308	0	0	0
T27	96461	0	0	0
T28	0	44946	0	0
T35	34966	23923	0	0
T73	0	617164	0	0
T91	0	25017	0	0
T102	0	2668	0	0
T159	0	2480	0	0
T163	0	3849	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486419960	485523430	0	0
T1	66844	66569	0	0
T2	13542	13268	0	0
T3	15893	15536	0	0
T4	263332	263308	0	0
T5	14662	14407	0	0
T6	548632	548605	0	0
T8	10671	10511	0	0
T9	7069	6986	0	0
T10	16135	15828	0	0
T11	15308	15021	0	0