Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

24004763

1

T1

2078

T2

386

T3

440

full_word

7935821

1

T1

1753

T2

194

T3

188

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31940294	1			T1	3831		T2	580		T3	628
auto[TlIntgErrCmd]	101	1			T255	3		T256	7		T257	3
auto[TlIntgErrData]	90	1			T255	2		T256	6		T257	1
auto[TlIntgErrBoth]	99	1			T255	5		T256	7		T257	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9696484

1

T1

3438

T2

346

T3

381

auto[1]

22244100

1

T1

393

T2

234

T3

247

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6176616	1			T1	1858		T2	251		T3	297
auto[TlIntgErrNone]	partial	auto[1]	17827876	1			T1	220		T2	135		T3	143
auto[TlIntgErrNone]	full_word	auto[0]	3519737	1			T1	1580		T2	95		T3	84
auto[TlIntgErrNone]	full_word	auto[1]	4416065	1			T1	173		T2	99		T3	104
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T255	2		T256	5		T257	3
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T255	1		T256	2		T334	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T338	1		T339	1		T340	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T335	1		T262	1		T341	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T255	1		T256	4		T263	5
auto[TlIntgErrData]	partial	auto[1]	47	1			T255	1		T256	2		T257	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T342	1		T336	2		T341	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T262	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T255	1		T256	3		T257	2
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T255	4		T256	3		T257	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T264	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T256	1		T263	1		T342	1