Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	96.96		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	462023525	7516053	0	0
check_regwen_rd_A	462023525	3826	0	0
check_timeout_rd_A	462023525	3596	0	0
check_trigger_regwen_rd_A	462023525	3731	0	0
consistency_check_period_rd_A	462023525	3954	0	0
creator_sw_cfg_read_lock_rd_A	462023525	3715	0	0
direct_access_address_rd_A	462023525	2773	0	0
direct_access_wdata_0_rd_A	462023525	1616	0	0
direct_access_wdata_1_rd_A	462023525	2365	0	0
integrity_check_period_rd_A	462023525	3700	0	0
intr_enable_rd_A	462023525	4705	0	0
owner_sw_cfg_read_lock_rd_A	462023525	3349	0	0
rot_creator_auth_codesign_read_lock_rd_A	462023525	3504	0	0
rot_creator_auth_state_read_lock_rd_A	462023525	3364	0	0
vendor_test_read_lock_rd_A	462023525	3438	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462023525	7516053	0	0
T8	391932	86816	0	0
T9	583797	124568	0	0
T13	0	80638	0	0
T17	41784	0	0	0
T18	0	85570	0	0
T19	0	90779	0	0
T30	0	54833	0	0
T48	11150	0	0	0
T91	48165	0	0	0
T100	12039	0	0	0
T105	17106	0	0	0
T106	13841	0	0	0
T115	0	158204	0	0
T120	0	33324	0	0
T198	26490	0	0	0
T226	60255	0	0	0
T265	0	56186	0	0
T266	0	60369	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462023525	3826	0	0
T13	515609	108	0	0
T20	0	63	0	0
T30	256088	0	0	0
T50	11433	0	0	0
T70	64162	0	0	0
T76	10259	0	0	0
T101	60498	0	0	0
T115	0	86	0	0
T178	0	71	0	0
T179	0	70	0	0
T184	11577	0	0	0
T185	12120	0	0	0
T209	11287	0	0	0
T237	0	82	0	0
T249	15740	0	0	0
T309	0	32	0	0
T317	0	85	0	0
T318	0	17	0	0
T319	0	63	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462023525	3596	0	0
T13	515609	81	0	0
T20	0	80	0	0
T30	256088	0	0	0
T50	11433	0	0	0
T70	64162	0	0	0
T76	10259	0	0	0
T101	60498	0	0	0
T115	0	96	0	0
T178	0	81	0	0
T179	0	71	0	0
T184	11577	0	0	0
T185	12120	0	0	0
T209	11287	0	0	0
T237	0	143	0	0
T249	15740	0	0	0
T309	0	22	0	0
T317	0	92	0	0
T318	0	31	0	0
T319	0	63	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462023525	3731	0	0
T13	515609	61	0	0
T20	0	40	0	0
T30	256088	0	0	0
T50	11433	0	0	0
T70	64162	0	0	0
T76	10259	0	0	0
T101	60498	0	0	0
T115	0	49	0	0
T178	0	74	0	0
T179	0	39	0	0
T184	11577	0	0	0
T185	12120	0	0	0
T209	11287	0	0	0
T237	0	115	0	0
T249	15740	0	0	0
T309	0	35	0	0
T317	0	122	0	0
T318	0	43	0	0
T319	0	44	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462023525	3954	0	0
T13	515609	101	0	0
T20	0	65	0	0
T30	256088	0	0	0
T50	11433	0	0	0
T70	64162	0	0	0
T76	10259	0	0	0
T101	60498	0	0	0
T115	0	120	0	0
T178	0	60	0	0
T179	0	84	0	0
T184	11577	0	0	0
T185	12120	0	0	0
T209	11287	0	0	0
T237	0	112	0	0
T249	15740	0	0	0
T309	0	7	0	0
T317	0	75	0	0
T318	0	27	0	0
T319	0	92	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462023525	3715	0	0
T13	515609	111	0	0
T20	0	57	0	0
T30	256088	0	0	0
T50	11433	0	0	0
T70	64162	0	0	0
T76	10259	0	0	0
T101	60498	0	0	0
T115	0	111	0	0
T178	0	72	0	0
T179	0	77	0	0
T184	11577	0	0	0
T185	12120	0	0	0
T209	11287	0	0	0
T237	0	119	0	0
T249	15740	0	0	0
T309	0	23	0	0
T317	0	76	0	0
T318	0	59	0	0
T319	0	39	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462023525	2773	0	0
T13	515609	94	0	0
T20	0	47	0	0
T30	256088	0	0	0
T50	11433	0	0	0
T70	64162	0	0	0
T76	10259	0	0	0
T101	60498	0	0	0
T115	0	77	0	0
T178	0	55	0	0
T179	0	112	0	0
T184	11577	0	0	0
T185	12120	0	0	0
T209	11287	0	0	0
T237	0	110	0	0
T249	15740	0	0	0
T309	0	19	0	0
T317	0	117	0	0
T318	0	62	0	0
T319	0	66	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462023525	1616	0	0
T13	515609	57	0	0
T20	0	54	0	0
T30	256088	0	0	0
T50	11433	0	0	0
T70	64162	0	0	0
T76	10259	0	0	0
T101	60498	0	0	0
T115	0	69	0	0
T178	0	52	0	0
T179	0	31	0	0
T184	11577	0	0	0
T185	12120	0	0	0
T209	11287	0	0	0
T237	0	94	0	0
T249	15740	0	0	0
T309	0	14	0	0
T317	0	57	0	0
T318	0	38	0	0
T319	0	33	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462023525	2365	0	0
T13	515609	85	0	0
T20	0	51	0	0
T30	256088	0	0	0
T50	11433	0	0	0
T70	64162	0	0	0
T76	10259	0	0	0
T101	60498	0	0	0
T115	0	74	0	0
T178	0	52	0	0
T179	0	53	0	0
T184	11577	0	0	0
T185	12120	0	0	0
T209	11287	0	0	0
T237	0	145	0	0
T249	15740	0	0	0
T309	0	14	0	0
T317	0	32	0	0
T318	0	49	0	0
T319	0	72	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462023525	3700	0	0
T13	515609	90	0	0
T20	0	51	0	0
T30	256088	0	0	0
T50	11433	0	0	0
T70	64162	0	0	0
T76	10259	0	0	0
T101	60498	0	0	0
T115	0	84	0	0
T178	0	36	0	0
T179	0	55	0	0
T184	11577	0	0	0
T185	12120	0	0	0
T209	11287	0	0	0
T237	0	46	0	0
T249	15740	0	0	0
T309	0	56	0	0
T317	0	133	0	0
T318	0	23	0	0
T319	0	51	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462023525	4705	0	0
T8	391932	0	0	0
T13	0	125	0	0
T16	110040	46	0	0
T20	0	61	0	0
T48	11150	0	0	0
T88	98941	0	0	0
T89	40728	0	0	0
T90	23742	0	0	0
T91	48165	0	0	0
T100	12039	0	0	0
T105	17106	0	0	0
T115	0	82	0	0
T178	0	65	0	0
T179	0	55	0	0
T198	26490	0	0	0
T223	0	26	0	0
T309	0	28	0	0
T317	0	144	0	0
T320	0	21	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462023525	3349	0	0
T13	515609	77	0	0
T20	0	54	0	0
T30	256088	0	0	0
T50	11433	0	0	0
T70	64162	0	0	0
T76	10259	0	0	0
T101	60498	0	0	0
T115	0	74	0	0
T178	0	76	0	0
T179	0	48	0	0
T184	11577	0	0	0
T185	12120	0	0	0
T209	11287	0	0	0
T237	0	84	0	0
T249	15740	0	0	0
T309	0	41	0	0
T317	0	85	0	0
T318	0	54	0	0
T319	0	58	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462023525	3504	0	0
T13	515609	87	0	0
T20	0	71	0	0
T30	256088	0	0	0
T50	11433	0	0	0
T70	64162	0	0	0
T76	10259	0	0	0
T101	60498	0	0	0
T115	0	101	0	0
T178	0	102	0	0
T179	0	87	0	0
T184	11577	0	0	0
T185	12120	0	0	0
T209	11287	0	0	0
T237	0	98	0	0
T249	15740	0	0	0
T309	0	24	0	0
T317	0	138	0	0
T318	0	37	0	0
T319	0	65	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462023525	3364	0	0
T13	515609	96	0	0
T20	0	45	0	0
T30	256088	0	0	0
T50	11433	0	0	0
T70	64162	0	0	0
T76	10259	0	0	0
T101	60498	0	0	0
T115	0	72	0	0
T178	0	68	0	0
T179	0	89	0	0
T184	11577	0	0	0
T185	12120	0	0	0
T209	11287	0	0	0
T237	0	116	0	0
T249	15740	0	0	0
T309	0	34	0	0
T317	0	72	0	0
T318	0	21	0	0
T319	0	45	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462023525	3438	0	0
T13	515609	110	0	0
T20	0	54	0	0
T30	256088	0	0	0
T50	11433	0	0	0
T70	64162	0	0	0
T76	10259	0	0	0
T101	60498	0	0	0
T115	0	101	0	0
T178	0	94	0	0
T179	0	63	0	0
T184	11577	0	0	0
T185	12120	0	0	0
T209	11287	0	0	0
T237	0	103	0	0
T249	15740	0	0	0
T309	0	27	0	0
T317	0	82	0	0
T318	0	58	0	0
T319	0	84	0	0