Line Coverage for Instance : tb.dut.u_edn_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 26 | 24 | 92.31 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 112 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 122 | 1 | 0 | 0.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 1 | 1 | 100.00 |
CONT_ASSIGN | 163 | 0 | 0 | |
CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 191 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
1 |
1 |
112 |
2 |
2 |
118 |
2 |
2 |
122 |
0 |
2 |
126 |
2 |
2 |
128 |
2 |
2 |
148 |
1 |
1 |
150 |
1 |
1 |
151 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
163 |
|
unreachable |
164 |
1 |
1 |
174 |
1 |
1 |
180 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
194 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_arb
| Total | Covered | Percent |
Conditions | 49 | 32 | 65.31 |
Logical | 49 | 32 | 65.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 118
EXPRESSION (req_i[0] & gen_normal_case.prio_mask_q[0])
----1--- ---------------2--------------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
LINE 118
EXPRESSION (req_i[1] & gen_normal_case.prio_mask_q[1])
----1--- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 126
EXPRESSION (req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | Excluded | |
vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T5,T6,T7 |
1 | 1 | 1 | Covered | T5,T6,T7 |
LINE 126
EXPRESSION (req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ready_i)
----1--- ----------------------------------2---------------------------------- ---3---
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[0])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T7 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T6,T7 |
LINE 128
EXPRESSION
Number Term
1 ((|req_i)) ? (gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))) : gen_normal_case.prio_mask_q[1])
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T7 |
LINE 128
SUB-EXPRESSION
Number Term
1 gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] |
2 (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i))))
-1- | -2- | Status | Tests |
0 | 0 | Not Covered | |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T7 |
LINE 128
SUB-EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~ready_i)))
----------------------------------1---------------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 148
EXPRESSION
Number Term
1 ((~gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) |
2 (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]))
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
LINE 148
SUB-EXPRESSION
Number Term
1 ((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])) &
2 gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Not Covered | |
LINE 150
EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T7 |
LINE 151
EXPRESSION (gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Not Covered | |
LINE 155
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION
Number Term
1 gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
----------------------------------1---------------------------------- -----------------------------2-----------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T6,T7 |
LINE 161
EXPRESSION (gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
----------------------------------1---------------------------------- ---------------------------2--------------------------
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 164
EXPRESSION (gen_normal_case.mask_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-----------------------------------1---------------------------------- ----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_edn_arb
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
155 |
2 |
2 |
100.00 |
TERNARY |
156 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
TERNARY |
128 |
2 |
2 |
100.00 |
IF |
191 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_tree.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 155 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 156 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 128 ((|req_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 191 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_arb
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459100430 |
458229571 |
0 |
0 |
T1 |
15038 |
14773 |
0 |
0 |
T2 |
13130 |
12895 |
0 |
0 |
T3 |
13472 |
13266 |
0 |
0 |
T4 |
21452 |
21277 |
0 |
0 |
T5 |
117845 |
116498 |
0 |
0 |
T6 |
28214 |
27655 |
0 |
0 |
T7 |
213200 |
208964 |
0 |
0 |
T10 |
14657 |
14492 |
0 |
0 |
T11 |
9610 |
9410 |
0 |
0 |
T12 |
92555 |
91892 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1147 |
1147 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459100430 |
292737 |
0 |
0 |
T5 |
117845 |
281 |
0 |
0 |
T6 |
28214 |
92 |
0 |
0 |
T7 |
213200 |
855 |
0 |
0 |
T8 |
0 |
2823 |
0 |
0 |
T10 |
14657 |
0 |
0 |
0 |
T11 |
9610 |
0 |
0 |
0 |
T12 |
92555 |
275 |
0 |
0 |
T16 |
110040 |
1851 |
0 |
0 |
T88 |
98941 |
372 |
0 |
0 |
T89 |
40728 |
46 |
0 |
0 |
T90 |
23742 |
0 |
0 |
0 |
T91 |
0 |
395 |
0 |
0 |
T105 |
0 |
91 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459100430 |
292737 |
0 |
0 |
T5 |
117845 |
281 |
0 |
0 |
T6 |
28214 |
92 |
0 |
0 |
T7 |
213200 |
855 |
0 |
0 |
T8 |
0 |
2823 |
0 |
0 |
T10 |
14657 |
0 |
0 |
0 |
T11 |
9610 |
0 |
0 |
0 |
T12 |
92555 |
275 |
0 |
0 |
T16 |
110040 |
1851 |
0 |
0 |
T88 |
98941 |
372 |
0 |
0 |
T89 |
40728 |
46 |
0 |
0 |
T90 |
23742 |
0 |
0 |
0 |
T91 |
0 |
395 |
0 |
0 |
T105 |
0 |
91 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459100430 |
458229571 |
0 |
0 |
T1 |
15038 |
14773 |
0 |
0 |
T2 |
13130 |
12895 |
0 |
0 |
T3 |
13472 |
13266 |
0 |
0 |
T4 |
21452 |
21277 |
0 |
0 |
T5 |
117845 |
116498 |
0 |
0 |
T6 |
28214 |
27655 |
0 |
0 |
T7 |
213200 |
208964 |
0 |
0 |
T10 |
14657 |
14492 |
0 |
0 |
T11 |
9610 |
9410 |
0 |
0 |
T12 |
92555 |
91892 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459100430 |
458229571 |
0 |
0 |
T1 |
15038 |
14773 |
0 |
0 |
T2 |
13130 |
12895 |
0 |
0 |
T3 |
13472 |
13266 |
0 |
0 |
T4 |
21452 |
21277 |
0 |
0 |
T5 |
117845 |
116498 |
0 |
0 |
T6 |
28214 |
27655 |
0 |
0 |
T7 |
213200 |
208964 |
0 |
0 |
T10 |
14657 |
14492 |
0 |
0 |
T11 |
9610 |
9410 |
0 |
0 |
T12 |
92555 |
91892 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459100430 |
292737 |
0 |
0 |
T5 |
117845 |
281 |
0 |
0 |
T6 |
28214 |
92 |
0 |
0 |
T7 |
213200 |
855 |
0 |
0 |
T8 |
0 |
2823 |
0 |
0 |
T10 |
14657 |
0 |
0 |
0 |
T11 |
9610 |
0 |
0 |
0 |
T12 |
92555 |
275 |
0 |
0 |
T16 |
110040 |
1851 |
0 |
0 |
T88 |
98941 |
372 |
0 |
0 |
T89 |
40728 |
46 |
0 |
0 |
T90 |
23742 |
0 |
0 |
0 |
T91 |
0 |
395 |
0 |
0 |
T105 |
0 |
91 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459100430 |
20681787 |
0 |
0 |
T5 |
117845 |
43292 |
0 |
0 |
T6 |
28214 |
2689 |
0 |
0 |
T7 |
213200 |
9430 |
0 |
0 |
T8 |
0 |
54929 |
0 |
0 |
T10 |
14657 |
0 |
0 |
0 |
T11 |
9610 |
0 |
0 |
0 |
T12 |
92555 |
4476 |
0 |
0 |
T16 |
110040 |
167433 |
0 |
0 |
T88 |
98941 |
11905 |
0 |
0 |
T89 |
40728 |
1813 |
0 |
0 |
T90 |
23742 |
0 |
0 |
0 |
T91 |
0 |
5247 |
0 |
0 |
T105 |
0 |
829 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459100430 |
437218152 |
0 |
0 |
T1 |
15038 |
14773 |
0 |
0 |
T2 |
13130 |
12895 |
0 |
0 |
T3 |
13472 |
13266 |
0 |
0 |
T4 |
21452 |
21277 |
0 |
0 |
T5 |
117845 |
72925 |
0 |
0 |
T6 |
28214 |
24873 |
0 |
0 |
T7 |
213200 |
198677 |
0 |
0 |
T10 |
14657 |
14492 |
0 |
0 |
T11 |
9610 |
9410 |
0 |
0 |
T12 |
92555 |
87141 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459100430 |
292737 |
0 |
0 |
T5 |
117845 |
281 |
0 |
0 |
T6 |
28214 |
92 |
0 |
0 |
T7 |
213200 |
855 |
0 |
0 |
T8 |
0 |
2823 |
0 |
0 |
T10 |
14657 |
0 |
0 |
0 |
T11 |
9610 |
0 |
0 |
0 |
T12 |
92555 |
275 |
0 |
0 |
T16 |
110040 |
1851 |
0 |
0 |
T88 |
98941 |
372 |
0 |
0 |
T89 |
40728 |
46 |
0 |
0 |
T90 |
23742 |
0 |
0 |
0 |
T91 |
0 |
395 |
0 |
0 |
T105 |
0 |
91 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459100430 |
292737 |
0 |
0 |
T5 |
117845 |
281 |
0 |
0 |
T6 |
28214 |
92 |
0 |
0 |
T7 |
213200 |
855 |
0 |
0 |
T8 |
0 |
2823 |
0 |
0 |
T10 |
14657 |
0 |
0 |
0 |
T11 |
9610 |
0 |
0 |
0 |
T12 |
92555 |
275 |
0 |
0 |
T16 |
110040 |
1851 |
0 |
0 |
T88 |
98941 |
372 |
0 |
0 |
T89 |
40728 |
46 |
0 |
0 |
T90 |
23742 |
0 |
0 |
0 |
T91 |
0 |
395 |
0 |
0 |
T105 |
0 |
91 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459100430 |
21011419 |
0 |
0 |
T5 |
117845 |
43573 |
0 |
0 |
T6 |
28214 |
2782 |
0 |
0 |
T7 |
213200 |
10287 |
0 |
0 |
T8 |
0 |
57752 |
0 |
0 |
T10 |
14657 |
0 |
0 |
0 |
T11 |
9610 |
0 |
0 |
0 |
T12 |
92555 |
4751 |
0 |
0 |
T16 |
110040 |
169294 |
0 |
0 |
T88 |
98941 |
12279 |
0 |
0 |
T89 |
40728 |
1859 |
0 |
0 |
T90 |
23742 |
0 |
0 |
0 |
T91 |
0 |
5644 |
0 |
0 |
T105 |
0 |
920 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459100430 |
20681787 |
0 |
0 |
T5 |
117845 |
43292 |
0 |
0 |
T6 |
28214 |
2689 |
0 |
0 |
T7 |
213200 |
9430 |
0 |
0 |
T8 |
0 |
54929 |
0 |
0 |
T10 |
14657 |
0 |
0 |
0 |
T11 |
9610 |
0 |
0 |
0 |
T12 |
92555 |
4476 |
0 |
0 |
T16 |
110040 |
167433 |
0 |
0 |
T88 |
98941 |
11905 |
0 |
0 |
T89 |
40728 |
1813 |
0 |
0 |
T90 |
23742 |
0 |
0 |
0 |
T91 |
0 |
5247 |
0 |
0 |
T105 |
0 |
829 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459100430 |
0 |
0 |
1147 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
459100430 |
458229571 |
0 |
0 |
T1 |
15038 |
14773 |
0 |
0 |
T2 |
13130 |
12895 |
0 |
0 |
T3 |
13472 |
13266 |
0 |
0 |
T4 |
21452 |
21277 |
0 |
0 |
T5 |
117845 |
116498 |
0 |
0 |
T6 |
28214 |
27655 |
0 |
0 |
T7 |
213200 |
208964 |
0 |
0 |
T10 |
14657 |
14492 |
0 |
0 |
T11 |
9610 |
9410 |
0 |
0 |
T12 |
92555 |
91892 |
0 |
0 |