Module Definition
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Module : prim_mubi8_sender
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock 83.33 50.00 100.00 100.00
tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock 83.33 50.00 100.00 100.00
tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock 83.33 50.00 100.00 100.00
tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock 83.33 50.00 100.00 100.00
tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock 83.33 50.00 100.00 100.00
tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock 83.33 50.00 100.00 100.00
tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock 83.33 50.00 100.00 100.00
tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock 83.33 50.00 100.00 100.00
tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock 83.33 50.00 100.00 100.00
tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock 83.33 50.00 100.00 100.00
tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock 83.33 50.00 100.00 100.00
tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock 83.33 50.00 100.00 100.00
tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock 83.33 50.00 100.00 100.00
tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock 83.33 50.00 100.00 100.00
tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock 83.33 50.00 100.00 100.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre 83.33 50.00 100.00 100.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre 83.33 50.00 100.00 100.00
tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock 100.00 100.00 100.00 100.00
tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock 100.00 100.00 100.00 100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock 100.00 100.00 100.00 100.00



Module Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 37.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 0.00 0.00



Module Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 37.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 0.00 0.00



Module Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 37.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 0.00 0.00



Module Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 37.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 0.00 0.00



Module Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 37.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 0.00 0.00



Module Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 37.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 0.00 0.00



Module Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 37.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 0.00 0.00



Module Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 37.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 0.00 0.00



Module Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 37.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 0.00 0.00



Module Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 37.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 0.00 0.00



Module Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 37.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 0.00 0.00



Module Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 37.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 0.00 0.00



Module Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 37.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 0.00 0.00



Module Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 37.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 0.00 0.00



Module Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 37.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 0.00 0.00



Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 37.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.90 96.91 100.00 95.24 100.00 82.35 gen_partitions[10].gen_lifecycle.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 0.00 0.00



Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 50.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 37.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.90 96.91 100.00 95.24 100.00 82.35 gen_partitions[10].gen_lifecycle.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 0.00 0.00



Module Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.18 94.16 96.15 96.96 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.23 100.00 100.00 85.00 100.00 96.15 gen_partitions[0].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.23 100.00 100.00 85.00 100.00 96.15 gen_partitions[0].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.23 100.00 100.00 85.00 100.00 96.15 gen_partitions[0].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 100.00 91.67 100.00 100.00 gen_partitions[1].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 100.00 91.67 100.00 100.00 gen_partitions[1].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 100.00 91.67 100.00 100.00 gen_partitions[1].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.75 100.00 97.06 91.67 100.00 100.00 gen_partitions[2].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.75 100.00 97.06 91.67 100.00 100.00 gen_partitions[2].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.75 100.00 97.06 91.67 100.00 100.00 gen_partitions[2].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 100.00 91.67 100.00 100.00 gen_partitions[3].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 100.00 91.67 100.00 100.00 gen_partitions[3].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 100.00 91.67 100.00 100.00 gen_partitions[3].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 100.00 91.67 100.00 100.00 gen_partitions[4].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 100.00 91.67 100.00 100.00 gen_partitions[4].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.33 100.00 100.00 91.67 100.00 100.00 gen_partitions[4].gen_unbuffered.u_part_unbuf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.82 97.64 95.24 92.00 96.36 82.86 gen_partitions[5].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.82 97.64 95.24 92.00 96.36 82.86 gen_partitions[5].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.82 97.64 95.24 92.00 96.36 82.86 gen_partitions[5].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.75 95.45 92.86 91.67 90.91 82.86 gen_partitions[6].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.75 95.45 92.86 91.67 90.91 82.86 gen_partitions[6].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.75 95.45 92.86 91.67 90.91 82.86 gen_partitions[6].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.65 98.00 93.75 91.67 95.38 94.44 gen_partitions[7].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.65 98.00 93.75 91.67 95.38 94.44 gen_partitions[7].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.65 98.00 93.75 91.67 95.38 94.44 gen_partitions[7].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.65 98.00 93.75 91.67 95.38 94.44 gen_partitions[7].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.09 98.00 93.75 88.89 95.38 94.44 gen_partitions[8].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.09 98.00 93.75 88.89 95.38 94.44 gen_partitions[8].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.09 98.00 93.75 88.89 95.38 94.44 gen_partitions[8].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.09 98.00 93.75 88.89 95.38 94.44 gen_partitions[8].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.65 98.00 93.75 91.67 95.38 94.44 gen_partitions[9].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.65 98.00 93.75 91.67 95.38 94.44 gen_partitions[9].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.65 98.00 93.75 91.67 95.38 94.44 gen_partitions[9].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00



Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.65 98.00 93.75 91.67 95.38 94.44 gen_partitions[9].gen_buffered.u_part_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_buf.u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi8_sender
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Module : prim_mubi8_sender
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_mubi8_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 2147483647 2147483647 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 857166 842061 0 0
T2 748410 735015 0 0
T3 767904 756162 0 0
T4 1222764 1212789 0 0
T5 6717165 6640386 0 0
T6 1608198 1576335 0 0
T7 12152400 11910948 0 0
T10 835449 826044 0 0
T11 547770 536370 0 0
T12 5275635 5237844 0 0

Line Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL6350.00
CONT_ASSIGN34100.00
CONT_ASSIGN48100.00
ALWAYS5533100.00
CONT_ASSIGN85100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 0 1
48 0 1
55 1 1
56 1 1
58 1 1
85 0 1


Branch Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL6350.00
CONT_ASSIGN34100.00
CONT_ASSIGN48100.00
ALWAYS5533100.00
CONT_ASSIGN85100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 0 1
48 0 1
55 1 1
56 1 1
58 1 1
85 0 1


Branch Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL6350.00
CONT_ASSIGN34100.00
CONT_ASSIGN48100.00
ALWAYS5533100.00
CONT_ASSIGN85100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 0 1
48 0 1
55 1 1
56 1 1
58 1 1
85 0 1


Branch Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL6350.00
CONT_ASSIGN34100.00
CONT_ASSIGN48100.00
ALWAYS5533100.00
CONT_ASSIGN85100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 0 1
48 0 1
55 1 1
56 1 1
58 1 1
85 0 1


Branch Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL6350.00
CONT_ASSIGN34100.00
CONT_ASSIGN48100.00
ALWAYS5533100.00
CONT_ASSIGN85100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 0 1
48 0 1
55 1 1
56 1 1
58 1 1
85 0 1


Branch Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL6350.00
CONT_ASSIGN34100.00
CONT_ASSIGN48100.00
ALWAYS5533100.00
CONT_ASSIGN85100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 0 1
48 0 1
55 1 1
56 1 1
58 1 1
85 0 1


Branch Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
TOTAL6350.00
CONT_ASSIGN34100.00
CONT_ASSIGN48100.00
ALWAYS5533100.00
CONT_ASSIGN85100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 0 1
48 0 1
55 1 1
56 1 1
58 1 1
85 0 1


Branch Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL6350.00
CONT_ASSIGN34100.00
CONT_ASSIGN48100.00
ALWAYS5533100.00
CONT_ASSIGN85100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 0 1
48 0 1
55 1 1
56 1 1
58 1 1
85 0 1


Branch Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
TOTAL6350.00
CONT_ASSIGN34100.00
CONT_ASSIGN48100.00
ALWAYS5533100.00
CONT_ASSIGN85100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 0 1
48 0 1
55 1 1
56 1 1
58 1 1
85 0 1


Branch Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL6350.00
CONT_ASSIGN34100.00
CONT_ASSIGN48100.00
ALWAYS5533100.00
CONT_ASSIGN85100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 0 1
48 0 1
55 1 1
56 1 1
58 1 1
85 0 1


Branch Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
TOTAL6350.00
CONT_ASSIGN34100.00
CONT_ASSIGN48100.00
ALWAYS5533100.00
CONT_ASSIGN85100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 0 1
48 0 1
55 1 1
56 1 1
58 1 1
85 0 1


Branch Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL6350.00
CONT_ASSIGN34100.00
CONT_ASSIGN48100.00
ALWAYS5533100.00
CONT_ASSIGN85100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 0 1
48 0 1
55 1 1
56 1 1
58 1 1
85 0 1


Branch Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
TOTAL6350.00
CONT_ASSIGN34100.00
CONT_ASSIGN48100.00
ALWAYS5533100.00
CONT_ASSIGN85100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 0 1
48 0 1
55 1 1
56 1 1
58 1 1
85 0 1


Branch Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[8].u_prim_mubi8_sender_read_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL6350.00
CONT_ASSIGN34100.00
CONT_ASSIGN48100.00
ALWAYS5533100.00
CONT_ASSIGN85100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 0 1
48 0 1
55 1 1
56 1 1
58 1 1
85 0 1


Branch Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
TOTAL6350.00
CONT_ASSIGN34100.00
CONT_ASSIGN48100.00
ALWAYS5533100.00
CONT_ASSIGN85100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 0 1
48 0 1
55 1 1
56 1 1
58 1 1
85 0 1


Branch Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[10].u_prim_mubi8_sender_read_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
TOTAL6350.00
CONT_ASSIGN34100.00
CONT_ASSIGN48100.00
ALWAYS5533100.00
CONT_ASSIGN85100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 0 1
48 0 1
55 1 1
56 1 1
58 1 1
85 0 1


Branch Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
TOTAL6350.00
CONT_ASSIGN34100.00
CONT_ASSIGN48100.00
ALWAYS5533100.00
CONT_ASSIGN85100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 0 1
48 0 1
55 1 1
56 1 1
58 1 1
85 0 1


Branch Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_bufs[9].u_prim_mubi8_sender_read_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4811100.00
ALWAYS5533100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
48 1 1
55 1 1
56 1 1
58 1 1
85 1 1


Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 55 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 459100430 458229571 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 459100430 458229571 0 0
T1 15038 14773 0 0
T2 13130 12895 0 0
T3 13472 13266 0 0
T4 21452 21277 0 0
T5 117845 116498 0 0
T6 28214 27655 0 0
T7 213200 208964 0 0
T10 14657 14492 0 0
T11 9610 9410 0 0
T12 92555 91892 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%