Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

22232524

1

T1

481

T2

1204

T3

883

full_word

7409112

1

T1

350

T2

205

T3

154

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	29641366	1			T1	831		T2	1409		T3	1037
auto[TlIntgErrCmd]	93	1			T280	8		T281	6		T282	3
auto[TlIntgErrData]	82	1			T280	7		T281	9		T282	9
auto[TlIntgErrBoth]	95	1			T280	5		T281	5		T282	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9223971

1

T1

500

T2

1170

T3

863

auto[1]

20417665

1

T1

331

T2

239

T3

174

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5876311	1			T1	286		T2	1064		T3	784
auto[TlIntgErrNone]	partial	auto[1]	16355961	1			T1	195		T2	140		T3	99
auto[TlIntgErrNone]	full_word	auto[0]	3347551	1			T1	214		T2	106		T3	79
auto[TlIntgErrNone]	full_word	auto[1]	4061543	1			T1	136		T2	99		T3	75
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T281	2		T386	1		T292	5
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T280	7		T281	4		T282	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T389	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T280	1		T391	1		-	-
auto[TlIntgErrData]	partial	auto[0]	34	1			T280	2		T281	5		T282	3
auto[TlIntgErrData]	partial	auto[1]	40	1			T280	5		T281	3		T282	6
auto[TlIntgErrData]	full_word	auto[0]	4	1			T390	1		T389	1		T392	2
auto[TlIntgErrData]	full_word	auto[1]	4	1			T281	1		T392	3		-	-
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T280	2		T281	1		T282	3
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T280	3		T281	4		T282	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T392	2		T286	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T291	1		T393	1		T392	1