Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.21	94.16	96.15	97.12		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	398892848	6852542	0	0
check_regwen_rd_A	398892848	2164	0	0
check_timeout_rd_A	398892848	1501	0	0
check_trigger_regwen_rd_A	398892848	2139	0	0
consistency_check_period_rd_A	398892848	2093	0	0
creator_sw_cfg_read_lock_rd_A	398892848	1628	0	0
direct_access_address_rd_A	398892848	1112	0	0
direct_access_wdata_0_rd_A	398892848	680	0	0
direct_access_wdata_1_rd_A	398892848	798	0	0
integrity_check_period_rd_A	398892848	2269	0	0
intr_enable_rd_A	398892848	2749	0	0
owner_sw_cfg_read_lock_rd_A	398892848	1442	0	0
rot_creator_auth_codesign_read_lock_rd_A	398892848	1497	0	0
rot_creator_auth_state_read_lock_rd_A	398892848	1350	0	0
vendor_test_read_lock_rd_A	398892848	1515	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398892848	6852542	0	0
T7	116035	21114	0	0
T8	956516	30148	0	0
T9	0	73065	0	0
T14	0	228592	0	0
T16	0	179358	0	0
T66	9519	0	0	0
T99	27135	0	0	0
T100	14483	0	0	0
T105	9863	0	0	0
T106	11502	0	0	0
T109	0	58249	0	0
T128	87866	0	0	0
T129	36960	0	0	0
T131	0	14789	0	0
T132	0	127717	0	0
T159	0	51480	0	0
T163	3998	0	0	0
T294	0	153107	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398892848	2164	0	0
T7	116035	11	0	0
T8	956516	0	0	0
T9	0	80	0	0
T66	9519	0	0	0
T99	27135	0	0	0
T100	14483	0	0	0
T105	9863	0	0	0
T106	11502	0	0	0
T128	87866	0	0	0
T129	36960	0	0	0
T163	3998	0	0	0
T270	0	78	0	0
T366	0	26	0	0
T367	0	61	0	0
T368	0	62	0	0
T369	0	89	0	0
T370	0	71	0	0
T371	0	128	0	0
T372	0	57	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398892848	1501	0	0
T7	116035	12	0	0
T8	956516	0	0	0
T9	0	48	0	0
T66	9519	0	0	0
T99	27135	0	0	0
T100	14483	0	0	0
T105	9863	0	0	0
T106	11502	0	0	0
T128	87866	0	0	0
T129	36960	0	0	0
T163	3998	0	0	0
T270	0	40	0	0
T366	0	13	0	0
T367	0	96	0	0
T368	0	71	0	0
T369	0	72	0	0
T370	0	85	0	0
T371	0	208	0	0
T372	0	82	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398892848	2139	0	0
T7	116035	27	0	0
T8	956516	0	0	0
T9	0	49	0	0
T66	9519	0	0	0
T99	27135	0	0	0
T100	14483	0	0	0
T105	9863	0	0	0
T106	11502	0	0	0
T128	87866	0	0	0
T129	36960	0	0	0
T163	3998	0	0	0
T270	0	96	0	0
T366	0	28	0	0
T367	0	38	0	0
T368	0	49	0	0
T369	0	74	0	0
T370	0	89	0	0
T371	0	166	0	0
T372	0	53	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398892848	2093	0	0
T7	116035	30	0	0
T8	956516	0	0	0
T9	0	27	0	0
T66	9519	0	0	0
T99	27135	0	0	0
T100	14483	0	0	0
T105	9863	0	0	0
T106	11502	0	0	0
T128	87866	0	0	0
T129	36960	0	0	0
T163	3998	0	0	0
T270	0	91	0	0
T366	0	27	0	0
T367	0	74	0	0
T368	0	26	0	0
T369	0	53	0	0
T370	0	89	0	0
T371	0	186	0	0
T372	0	27	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398892848	1628	0	0
T7	116035	39	0	0
T8	956516	0	0	0
T9	0	73	0	0
T66	9519	0	0	0
T99	27135	0	0	0
T100	14483	0	0	0
T105	9863	0	0	0
T106	11502	0	0	0
T128	87866	0	0	0
T129	36960	0	0	0
T163	3998	0	0	0
T270	0	93	0	0
T366	0	6	0	0
T367	0	98	0	0
T368	0	56	0	0
T369	0	133	0	0
T370	0	88	0	0
T371	0	142	0	0
T372	0	28	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398892848	1112	0	0
T7	116035	20	0	0
T8	956516	0	0	0
T9	0	32	0	0
T66	9519	0	0	0
T99	27135	0	0	0
T100	14483	0	0	0
T105	9863	0	0	0
T106	11502	0	0	0
T128	87866	0	0	0
T129	36960	0	0	0
T163	3998	0	0	0
T270	0	73	0	0
T366	0	20	0	0
T367	0	123	0	0
T368	0	42	0	0
T369	0	110	0	0
T370	0	66	0	0
T371	0	185	0	0
T372	0	61	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398892848	680	0	0
T7	116035	10	0	0
T8	956516	0	0	0
T9	0	59	0	0
T66	9519	0	0	0
T99	27135	0	0	0
T100	14483	0	0	0
T105	9863	0	0	0
T106	11502	0	0	0
T128	87866	0	0	0
T129	36960	0	0	0
T163	3998	0	0	0
T270	0	39	0	0
T366	0	5	0	0
T367	0	28	0	0
T368	0	31	0	0
T369	0	58	0	0
T370	0	33	0	0
T371	0	136	0	0
T372	0	59	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398892848	798	0	0
T7	116035	27	0	0
T8	956516	0	0	0
T9	0	31	0	0
T66	9519	0	0	0
T99	27135	0	0	0
T100	14483	0	0	0
T105	9863	0	0	0
T106	11502	0	0	0
T128	87866	0	0	0
T129	36960	0	0	0
T163	3998	0	0	0
T270	0	84	0	0
T304	0	38	0	0
T367	0	56	0	0
T368	0	35	0	0
T369	0	108	0	0
T370	0	50	0	0
T371	0	107	0	0
T372	0	28	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398892848	2269	0	0
T7	116035	42	0	0
T8	956516	0	0	0
T9	0	41	0	0
T66	9519	0	0	0
T99	27135	0	0	0
T100	14483	0	0	0
T105	9863	0	0	0
T106	11502	0	0	0
T128	87866	0	0	0
T129	36960	0	0	0
T163	3998	0	0	0
T270	0	83	0	0
T366	0	21	0	0
T367	0	74	0	0
T368	0	54	0	0
T369	0	73	0	0
T370	0	24	0	0
T371	0	159	0	0
T372	0	47	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398892848	2749	0	0
T7	116035	33	0	0
T8	956516	0	0	0
T9	0	96	0	0
T66	9519	0	0	0
T99	27135	0	0	0
T100	14483	0	0	0
T105	9863	0	0	0
T106	11502	0	0	0
T128	87866	0	0	0
T129	36960	0	0	0
T163	3998	0	0	0
T269	0	15	0	0
T270	0	70	0	0
T366	0	13	0	0
T367	0	69	0	0
T368	0	52	0	0
T369	0	49	0	0
T370	0	78	0	0
T373	0	23	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398892848	1442	0	0
T7	116035	26	0	0
T8	956516	0	0	0
T9	0	76	0	0
T66	9519	0	0	0
T99	27135	0	0	0
T100	14483	0	0	0
T105	9863	0	0	0
T106	11502	0	0	0
T128	87866	0	0	0
T129	36960	0	0	0
T163	3998	0	0	0
T270	0	75	0	0
T366	0	23	0	0
T367	0	101	0	0
T368	0	21	0	0
T369	0	80	0	0
T370	0	42	0	0
T371	0	144	0	0
T372	0	69	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398892848	1497	0	0
T7	116035	46	0	0
T8	956516	0	0	0
T9	0	38	0	0
T66	9519	0	0	0
T99	27135	0	0	0
T100	14483	0	0	0
T105	9863	0	0	0
T106	11502	0	0	0
T128	87866	0	0	0
T129	36960	0	0	0
T163	3998	0	0	0
T270	0	55	0	0
T366	0	33	0	0
T367	0	75	0	0
T368	0	30	0	0
T369	0	123	0	0
T370	0	58	0	0
T371	0	153	0	0
T372	0	64	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398892848	1350	0	0
T7	116035	19	0	0
T8	956516	0	0	0
T9	0	91	0	0
T66	9519	0	0	0
T99	27135	0	0	0
T100	14483	0	0	0
T105	9863	0	0	0
T106	11502	0	0	0
T128	87866	0	0	0
T129	36960	0	0	0
T163	3998	0	0	0
T270	0	86	0	0
T366	0	17	0	0
T367	0	59	0	0
T368	0	29	0	0
T369	0	109	0	0
T370	0	41	0	0
T371	0	115	0	0
T372	0	44	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398892848	1515	0	0
T7	116035	38	0	0
T8	956516	0	0	0
T9	0	37	0	0
T66	9519	0	0	0
T99	27135	0	0	0
T100	14483	0	0	0
T105	9863	0	0	0
T106	11502	0	0	0
T128	87866	0	0	0
T129	36960	0	0	0
T163	3998	0	0	0
T270	0	49	0	0
T366	0	44	0	0
T367	0	92	0	0
T368	0	74	0	0
T369	0	116	0	0
T370	0	34	0	0
T371	0	109	0	0
T372	0	72	0	0