Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.21	94.16	96.15	97.12		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.21	94.16	96.15	97.12		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.21	94.16	96.15	97.12		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T2,T3,T11
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T165,T166
1	Covered	T165,T166

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T11

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T97
1	1	Covered	T2,T3,T11

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T97

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T97

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T11
ReadWaitSt	252	Covered	T2,T3,T11
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T2,T3,T11
InitSt->ErrorSt	315	Covered	T208,T209,T210
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T107,T211,T212
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T5,T7,T8
ReadSt->ReadWaitSt	252	Covered	T2,T3,T11
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T2,T3,T11
ResetSt->ErrorSt	315	Covered	T66,T67,T68
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T5,T7,T8
CheckFailError	317	Covered	T165,T166
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T8,T161,T14
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T5,T7,T8
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T165,T166
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T5,T7,T8
NoError->CheckFailError	317	Covered	T165,T166
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T11

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T11

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T13,T97
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T11
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T8,T15,T159
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T7,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T97,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T97,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T165,T166
1	0	Covered	T165,T166
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T13,T97,T128
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	396154897	395268497	0	0
DigestKnown_A	396154897	395268497	0	0
DigestOffsetMustBeRepresentable_A	1143	1143	0	0
EccErrorState_A	396154897	6364	0	0
ErrorKnown_A	396154897	395268497	0	0
FsmStateKnown_A	396154897	395268497	0	0
InitDoneKnown_A	396154897	395268497	0	0
InitReadLocksPartition_A	396154897	79579431	0	0
InitWriteLocksPartition_A	396154897	79579431	0	0
OffsetMustBeBlockAligned_A	1143	1143	0	0
OtpAddrKnown_A	396154897	395268497	0	0
OtpCmdKnown_A	396154897	395268497	0	0
OtpErrorState_A	396154897	0	0	0
OtpReqKnown_A	396154897	395268497	0	0
OtpSizeKnown_A	396154897	395268497	0	0
OtpWdataKnown_A	396154897	395268497	0	0
ReadLockPropagation_A	396154897	153776143	0	0
SizeMustBeBlockAligned_A	1143	1143	0	0
TlulGntKnown_A	396154897	395268497	0	0
TlulRdataKnown_A	396154897	395268497	0	0
TlulReadOnReadLock_A	396154897	7615	0	0
TlulRerrorKnown_A	396154897	395268497	0	0
TlulRvalidKnown_A	396154897	395268497	0	0
WriteLockPropagation_A	396154897	2352580	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	396154897	25775823	0	0
u_state_regs_A	396154897	395268497	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	6364	0	0
T60	15357	0	0	0
T165	18056	3507	0	0
T166	0	2857	0	0
T173	30503	0	0	0
T174	10688	0	0	0
T175	10070	0	0	0
T176	13377	0	0	0
T177	11878	0	0	0
T178	169272	0	0	0
T179	149752	0	0	0
T180	9169	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	79579431	0	0
T1	18106	10272	0	0
T2	11436	4662	0	0
T3	14045	5280	0	0
T4	99681	861	0	0
T5	76871	2226	0	0
T6	38894	1575	0	0
T10	5022	131	0	0
T11	12539	4222	0	0
T12	26876	387	0	0
T13	10539	4513	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	79579431	0	0
T1	18106	10272	0	0
T2	11436	4662	0	0
T3	14045	5280	0	0
T4	99681	861	0	0
T5	76871	2226	0	0
T6	38894	1575	0	0
T10	5022	131	0	0
T11	12539	4222	0	0
T12	26876	387	0	0
T13	10539	4513	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	153776143	0	0
T4	99681	5282	0	0
T5	76871	3238	0	0
T6	38894	0	0	0
T7	116035	115457	0	0
T8	0	369468	0	0
T11	12539	0	0	0
T12	26876	0	0	0
T13	10539	0	0	0
T26	0	40862	0	0
T27	28988	0	0	0
T36	0	43061	0	0
T37	0	9995	0	0
T44	11762	0	0	0
T61	0	2706	0	0
T97	138219	0	0	0
T107	0	3275	0	0
T128	0	9068	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	7615	0	0
T1	18106	7	0	0
T2	11436	0	0	0
T3	14045	0	0	0
T4	99681	0	0	0
T5	76871	1	0	0
T6	38894	0	0	0
T7	0	17	0	0
T8	0	35	0	0
T10	5022	0	0	0
T11	12539	0	0	0
T12	26876	0	0	0
T13	10539	0	0	0
T26	0	15	0	0
T36	0	14	0	0
T97	0	9	0	0
T107	0	18	0	0
T128	0	10	0	0
T129	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	2352580	0	0
T5	76871	7072	0	0
T6	38894	0	0	0
T7	116035	0	0	0
T12	26876	0	0	0
T13	10539	0	0	0
T15	0	16069	0	0
T27	28988	0	0	0
T36	0	19653	0	0
T37	0	5460	0	0
T44	11762	0	0	0
T86	0	17495	0	0
T95	0	13376	0	0
T97	138219	0	0	0
T99	27135	0	0	0
T117	0	44113	0	0
T128	87866	0	0	0
T198	0	1813	0	0
T199	0	2661	0	0
T200	0	10822	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	25775823	0	0
T5	76871	67672	0	0
T6	38894	0	0	0
T7	116035	0	0	0
T12	26876	0	0	0
T13	10539	4003	0	0
T26	0	136358	0	0
T27	28988	0	0	0
T36	0	148852	0	0
T37	0	107350	0	0
T41	0	6992	0	0
T44	11762	0	0	0
T97	138219	7777	0	0
T99	27135	0	0	0
T105	0	2204	0	0
T107	0	3027	0	0
T125	0	4857	0	0
T128	87866	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T167,T168,T33

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T4,T11
1	Covered	T97,T128,T26

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T66,T150,T166
1	Covered	T66,T150,T166

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T11

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T97
1	1	Covered	T2,T4,T11

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T4,T11
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T4,T11
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T97,T128

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T97,T128

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T4,T11
ReadWaitSt	252	Covered	T2,T4,T11
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T2,T4,T11
InitSt->ErrorSt	315	Covered	T107,T211,T212
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T106,T172,T181
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T5,T7,T8
ReadSt->ReadWaitSt	252	Covered	T2,T4,T11
ReadWaitSt->ErrorSt	276	Covered	T156,T192,T213
ReadWaitSt->IdleSt	270	Covered	T2,T4,T11
ResetSt->ErrorSt	315	Covered	T66,T67,T68
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T5,T7,T8
CheckFailError	317	Covered	T66,T150,T166
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T97,T128,T26
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T8,T14,T15
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T5,T7,T8
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T66,T150,T166
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T97,T128,T167
MacroEccCorrError->NoError	235	Covered	T26,T64,T55
NoError->AccessError	256	Covered	T5,T7,T8
NoError->CheckFailError	317	Covered	T66,T150,T166
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Covered	T97,T128,T26

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T11

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T11

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T97,T128
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T167,T168,T33
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T106,T172,T181
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T4,T11
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T4,T11
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T5,T15,T214
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T5,T7,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T97,T128,T26
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T4,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T156,T192,T213
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T4,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T97,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T97,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T66,T150,T166
1	0	Covered	T66,T150,T166
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	396154897	395268497	0	0
DigestKnown_A	396154897	395268497	0	0
DigestOffsetMustBeRepresentable_A	1143	1143	0	0
EccErrorState_A	396154897	9686	0	0
ErrorKnown_A	396154897	395268497	0	0
FsmStateKnown_A	396154897	395268497	0	0
InitDoneKnown_A	396154897	395268497	0	0
InitReadLocksPartition_A	396154897	79766069	0	0
InitWriteLocksPartition_A	396154897	79766069	0	0
OffsetMustBeBlockAligned_A	1143	1143	0	0
OtpAddrKnown_A	396154897	395268497	0	0
OtpCmdKnown_A	396154897	395268497	0	0
OtpErrorState_A	396154897	79	0	0
OtpReqKnown_A	396154897	395268497	0	0
OtpSizeKnown_A	396154897	395268497	0	0
OtpWdataKnown_A	396154897	395268497	0	0
ReadLockPropagation_A	396154897	147644108	0	0
SizeMustBeBlockAligned_A	1143	1143	0	0
TlulGntKnown_A	396154897	395268497	0	0
TlulRdataKnown_A	396154897	395268497	0	0
TlulReadOnReadLock_A	396154897	7745	0	0
TlulRerrorKnown_A	396154897	395268497	0	0
TlulRvalidKnown_A	396154897	395268497	0	0
WriteLockPropagation_A	396154897	2417848	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	396154897	25047886	0	0
u_state_regs_A	396154897	395268497	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	9686	0	0
T8	956516	0	0	0
T26	154193	0	0	0
T36	163935	0	0	0
T66	9519	2765	0	0
T100	14483	0	0	0
T105	9863	0	0	0
T106	11502	0	0	0
T107	23524	0	0	0
T129	36960	0	0	0
T150	0	4064	0	0
T163	3998	0	0	0
T166	0	2857	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	79766069	0	0
T1	18106	10323	0	0
T2	11436	4696	0	0
T3	14045	5331	0	0
T4	99681	1167	0	0
T5	76871	2549	0	0
T6	38894	1762	0	0
T10	5022	148	0	0
T11	12539	4256	0	0
T12	26876	523	0	0
T13	10539	4547	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	79766069	0	0
T1	18106	10323	0	0
T2	11436	4696	0	0
T3	14045	5331	0	0
T4	99681	1167	0	0
T5	76871	2549	0	0
T6	38894	1762	0	0
T10	5022	148	0	0
T11	12539	4256	0	0
T12	26876	523	0	0
T13	10539	4547	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	79	0	0
T26	154193	0	0	0
T36	163935	0	0	0
T37	132306	0	0	0
T41	19593	0	0	0
T61	21983	0	0	0
T101	11770	0	0	0
T102	25435	0	0	0
T106	11502	1	0	0
T107	23524	0	0	0
T156	0	1	0	0
T172	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T190	0	1	0	0
T197	8781	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	147644108	0	0
T4	99681	3728	0	0
T5	76871	876	0	0
T6	38894	0	0	0
T7	116035	123978	0	0
T8	0	249540	0	0
T11	12539	0	0	0
T12	26876	0	0	0
T13	10539	0	0	0
T26	0	51471	0	0
T27	28988	0	0	0
T36	0	48854	0	0
T37	0	16818	0	0
T44	11762	0	0	0
T97	138219	3976	0	0
T107	0	3273	0	0
T128	0	9058	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	7745	0	0
T1	18106	7	0	0
T2	11436	0	0	0
T3	14045	0	0	0
T4	99681	0	0	0
T5	76871	2	0	0
T6	38894	0	0	0
T7	0	15	0	0
T8	0	45	0	0
T10	5022	0	0	0
T11	12539	0	0	0
T12	26876	0	0	0
T13	10539	0	0	0
T26	0	12	0	0
T36	0	10	0	0
T97	0	6	0	0
T107	0	20	0	0
T128	0	4	0	0
T129	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	2417848	0	0
T5	76871	298	0	0
T6	38894	0	0	0
T7	116035	0	0	0
T12	26876	0	0	0
T13	10539	0	0	0
T15	0	35519	0	0
T26	0	27920	0	0
T27	28988	0	0	0
T36	0	43901	0	0
T37	0	8625	0	0
T44	11762	0	0	0
T86	0	10290	0	0
T92	0	34107	0	0
T93	0	10890	0	0
T95	0	13376	0	0
T96	0	2871	0	0
T97	138219	0	0	0
T99	27135	0	0	0
T128	87866	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	25047886	0	0
T5	76871	45849	0	0
T6	38894	0	0	0
T7	116035	0	0	0
T12	26876	0	0	0
T13	10539	0	0	0
T26	0	136171	0	0
T27	28988	0	0	0
T36	0	148580	0	0
T37	0	119782	0	0
T44	11762	0	0	0
T61	0	11833	0	0
T97	138219	7760	0	0
T99	27135	0	0	0
T107	0	2993	0	0
T128	87866	16595	0	0
T206	0	15457	0	0
T207	0	8122	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T105,T41,T76

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T128,T26,T162

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T21,T22

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T169,T170,T166
1	Covered	T169,T170,T166

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T97
1	1	Covered	T2,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T107,T36

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T107,T36

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T2,T3
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T2,T3,T4
ReadWaitSt	252	Covered	T2,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T2,T3
IdleSt->ReadSt	236	Covered	T2,T3,T4
InitSt->ErrorSt	315	Covered	T107,T211,T212
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T106,T172,T181
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T4,T7,T8
ReadSt->ReadWaitSt	252	Covered	T2,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T97,T192,T194
ReadWaitSt->IdleSt	270	Covered	T2,T3,T4
ResetSt->ErrorSt	315	Covered	T66,T67,T68
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T4,T7,T8
CheckFailError	317	Covered	T169,T170,T166
FsmStateError	289	Covered	T1,T2,T3
MacroEccCorrError	221	Covered	T128,T105,T26
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T8,T109,T215
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T4,T7,T8
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T169,T170,T166
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T2,T3
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T128,T105,T41
MacroEccCorrError->NoError	235	Covered	T26,T64,T55
NoError->AccessError	256	Covered	T4,T7,T8
NoError->CheckFailError	317	Covered	T169,T170,T166
NoError->FsmStateError	289	Covered	T1,T2,T3
NoError->MacroEccCorrError	221	Covered	T128,T105,T26

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T107,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T105,T41,T76
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T185,T188,T189
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T5,T8,T15
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T4,T7,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T128,T26,T162
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T97,T192,T194
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T97,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T97,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T169,T170,T166
1	0	Covered	T169,T170,T166
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	396154897	395268497	0	0
DigestKnown_A	396154897	395268497	0	0
DigestOffsetMustBeRepresentable_A	1143	1143	0	0
EccErrorState_A	396154897	8529	0	0
ErrorKnown_A	396154897	395268497	0	0
FsmStateKnown_A	396154897	395268497	0	0
InitDoneKnown_A	396154897	395268497	0	0
InitReadLocksPartition_A	396154897	79951445	0	0
InitWriteLocksPartition_A	396154897	79951445	0	0
OffsetMustBeBlockAligned_A	1143	1143	0	0
OtpAddrKnown_A	396154897	395268497	0	0
OtpCmdKnown_A	396154897	395268497	0	0
OtpErrorState_A	396154897	38	0	0
OtpReqKnown_A	396154897	395268497	0	0
OtpSizeKnown_A	396154897	395268497	0	0
OtpWdataKnown_A	396154897	395268497	0	0
ReadLockPropagation_A	396154897	152951685	0	0
SizeMustBeBlockAligned_A	1143	1143	0	0
TlulGntKnown_A	396154897	395268497	0	0
TlulRdataKnown_A	396154897	395268497	0	0
TlulReadOnReadLock_A	396154897	8095	0	0
TlulRerrorKnown_A	396154897	395268497	0	0
TlulRvalidKnown_A	396154897	395268497	0	0
WriteLockPropagation_A	396154897	1422425	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	396154897	17048174	0	0
u_state_regs_A	396154897	395268497	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	8529	0	0
T166	0	2857	0	0
T169	9779	3337	0	0
T170	0	2335	0	0
T216	26336	0	0	0
T217	44564	0	0	0
T218	708420	0	0	0
T219	37892	0	0	0
T220	14684	0	0	0
T221	13677	0	0	0
T222	13523	0	0	0
T223	12734	0	0	0
T224	123413	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	79951445	0	0
T1	18106	10374	0	0
T2	11436	4730	0	0
T3	14045	5382	0	0
T4	99681	1473	0	0
T5	76871	2872	0	0
T6	38894	1949	0	0
T10	5022	165	0	0
T11	12539	4290	0	0
T12	26876	659	0	0
T13	10539	4581	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	79951445	0	0
T1	18106	10374	0	0
T2	11436	4730	0	0
T3	14045	5382	0	0
T4	99681	1473	0	0
T5	76871	2872	0	0
T6	38894	1949	0	0
T10	5022	165	0	0
T11	12539	4290	0	0
T12	26876	659	0	0
T13	10539	4581	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	38	0	0
T7	116035	0	0	0
T44	11762	0	0	0
T66	9519	0	0	0
T97	138219	1	0	0
T99	27135	0	0	0
T100	14483	0	0	0
T105	9863	0	0	0
T128	87866	0	0	0
T129	36960	0	0	0
T163	3998	0	0	0
T185	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0
T196	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	152951685	0	0
T4	99681	8289	0	0
T5	76871	2462	0	0
T6	38894	0	0	0
T7	116035	140363	0	0
T8	0	342986	0	0
T11	12539	0	0	0
T12	26876	0	0	0
T13	10539	0	0	0
T26	0	32498	0	0
T27	28988	0	0	0
T36	0	54294	0	0
T37	0	17707	0	0
T44	11762	0	0	0
T97	138219	3968	0	0
T107	0	1634	0	0
T128	0	9048	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	8095	0	0
T1	18106	9	0	0
T2	11436	0	0	0
T3	14045	0	0	0
T4	99681	3	0	0
T5	76871	0	0	0
T6	38894	0	0	0
T7	0	18	0	0
T8	0	39	0	0
T10	5022	0	0	0
T11	12539	0	0	0
T12	26876	0	0	0
T13	10539	0	0	0
T26	0	16	0	0
T36	0	10	0	0
T61	0	3	0	0
T97	0	5	0	0
T107	0	13	0	0
T128	0	14	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	1422425	0	0
T5	76871	684	0	0
T6	38894	0	0	0
T7	116035	0	0	0
T12	26876	0	0	0
T13	10539	0	0	0
T15	0	16836	0	0
T27	28988	0	0	0
T44	11762	0	0	0
T86	0	17947	0	0
T92	0	9337	0	0
T97	138219	0	0	0
T99	27135	0	0	0
T117	0	24149	0	0
T121	0	13727	0	0
T128	87866	0	0	0
T198	0	3132	0	0
T199	0	5644	0	0
T201	0	6622	0	0
T202	0	1123	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	17048174	0	0
T5	76871	67060	0	0
T6	38894	0	0	0
T7	116035	0	0	0
T12	26876	0	0	0
T13	10539	0	0	0
T27	28988	0	0	0
T36	0	148308	0	0
T44	11762	0	0	0
T61	0	11782	0	0
T90	0	22932	0	0
T91	0	17557	0	0
T92	0	107516	0	0
T97	138219	0	0	0
T98	0	83533	0	0
T99	27135	0	0	0
T107	0	2959	0	0
T114	0	8424	0	0
T128	87866	0	0	0
T207	0	8088	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396154897	395268497	0	0
T1	18106	17835	0	0
T2	11436	11165	0	0
T3	14045	13772	0	0
T4	99681	98284	0	0
T5	76871	75275	0	0
T6	38894	38062	0	0
T10	5022	4970	0	0
T11	12539	12272	0	0
T12	26876	26369	0	0
T13	10539	10271	0	0