Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7898676	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7751131

1

T1

34

T2

22

T3

120963

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9062503	1			T1	1		T2	1		T3	79806
values[0x0]	2504037	1			T1	49		T2	37		T3	45335
values[0x1]	4083267	1			T1	59		T2	28		T3	79771

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5107704	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

10542103

1

T1

43

T2

30

T3

159215

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54171	1			T3	776		T7	53		T4	5
valid_sources[0x01]	53613	1			T3	787		T7	57		T4	11
valid_sources[0x02]	57295	1			T2	3		T3	754		T7	41
valid_sources[0x03]	54661	1			T3	756		T7	58		T4	15
valid_sources[0x04]	66931	1			T3	837		T7	65		T4	8
valid_sources[0x05]	63441	1			T3	794		T7	39		T4	6
valid_sources[0x06]	59101	1			T3	796		T7	49		T4	7
valid_sources[0x07]	55184	1			T3	813		T7	41		T4	8
valid_sources[0x08]	72848	1			T3	768		T7	38		T4	9
valid_sources[0x09]	56298	1			T3	769		T7	38		T4	6
valid_sources[0x0a]	58750	1			T3	777		T7	59		T4	14
valid_sources[0x0b]	66333	1			T3	766		T7	51		T4	19
valid_sources[0x0c]	59764	1			T3	834		T7	53		T4	13
valid_sources[0x0d]	55440	1			T3	828		T7	52		T4	6
valid_sources[0x0e]	55018	1			T1	2		T3	801		T7	48
valid_sources[0x0f]	54324	1			T3	817		T7	42		T4	12
valid_sources[0x10]	58262	1			T3	782		T7	60		T4	15
valid_sources[0x11]	54037	1			T3	829		T7	63		T4	14
valid_sources[0x12]	57929	1			T3	791		T7	58		T4	12
valid_sources[0x13]	57468	1			T3	781		T7	48		T4	14
valid_sources[0x14]	52621	1			T2	3		T3	786		T7	45
valid_sources[0x15]	64043	1			T3	768		T7	54		T4	13
valid_sources[0x16]	54989	1			T3	796		T7	53		T4	16
valid_sources[0x17]	54079	1			T3	833		T7	52		T4	19
valid_sources[0x18]	54254	1			T2	1		T3	762		T7	38
valid_sources[0x19]	51129	1			T3	760		T7	46		T4	7
valid_sources[0x1a]	58449	1			T3	755		T7	38		T4	17
valid_sources[0x1b]	67884	1			T1	1		T3	810		T7	36
valid_sources[0x1c]	63113	1			T3	738		T7	52		T4	13
valid_sources[0x1d]	56326	1			T3	812		T7	71		T4	5
valid_sources[0x1e]	63368	1			T3	761		T7	57		T4	20
valid_sources[0x1f]	66093	1			T2	5		T3	810		T7	57
valid_sources[0x20]	57635	1			T1	3		T3	839		T7	34
valid_sources[0x21]	58412	1			T3	823		T7	50		T4	16
valid_sources[0x22]	56836	1			T3	818		T7	34		T4	10
valid_sources[0x23]	61147	1			T3	741		T7	41		T4	9
valid_sources[0x24]	57689	1			T1	1		T3	798		T7	41
valid_sources[0x25]	56652	1			T3	753		T7	50		T4	7
valid_sources[0x26]	57471	1			T1	1		T3	854		T7	42
valid_sources[0x27]	55251	1			T3	820		T7	60		T4	13
valid_sources[0x28]	57067	1			T3	802		T7	46		T4	11
valid_sources[0x29]	55487	1			T3	869		T7	44		T4	19
valid_sources[0x2a]	59006	1			T2	2		T3	817		T7	68
valid_sources[0x2b]	61874	1			T3	759		T7	44		T4	11
valid_sources[0x2c]	138675	1			T3	781		T7	63		T4	15
valid_sources[0x2d]	65642	1			T3	732		T7	42		T4	16
valid_sources[0x2e]	56442	1			T3	786		T7	44		T4	16
valid_sources[0x2f]	52859	1			T3	772		T7	64		T4	4
valid_sources[0x30]	53629	1			T3	817		T7	45		T4	17
valid_sources[0x31]	60612	1			T3	769		T7	68		T4	11
valid_sources[0x32]	67281	1			T3	825		T7	39		T4	17
valid_sources[0x33]	57548	1			T1	1		T3	789		T7	38
valid_sources[0x34]	59348	1			T3	845		T7	51		T4	8
valid_sources[0x35]	61541	1			T3	758		T7	33		T4	13
valid_sources[0x36]	55433	1			T3	776		T7	37		T4	10
valid_sources[0x37]	63936	1			T3	780		T7	51		T4	13
valid_sources[0x38]	53866	1			T3	820		T7	56		T4	11
valid_sources[0x39]	54230	1			T3	831		T7	40		T4	16
valid_sources[0x3a]	55126	1			T3	867		T7	47		T4	6
valid_sources[0x3b]	55735	1			T3	793		T7	49		T4	19
valid_sources[0x3c]	61967	1			T3	840		T7	47		T4	15
valid_sources[0x3d]	58361	1			T3	808		T7	42		T4	17
valid_sources[0x3e]	61750	1			T3	793		T7	44		T4	11
valid_sources[0x3f]	53206	1			T1	3		T3	803		T7	49
valid_sources[0x40]	72176	1			T3	823		T7	28		T4	14
valid_sources[0x41]	62377	1			T3	764		T7	53		T4	15
valid_sources[0x42]	52522	1			T3	785		T7	45		T4	12
valid_sources[0x43]	55772	1			T3	850		T7	47		T4	15
valid_sources[0x44]	55960	1			T3	833		T7	38		T4	21
valid_sources[0x45]	60991	1			T3	808		T7	47		T4	7
valid_sources[0x46]	56130	1			T3	823		T7	54		T4	14
valid_sources[0x47]	56679	1			T3	825		T7	46		T4	9
valid_sources[0x48]	61873	1			T3	854		T7	49		T4	16
valid_sources[0x49]	65764	1			T3	773		T7	45		T4	10
valid_sources[0x4a]	69999	1			T3	811		T7	45		T4	17
valid_sources[0x4b]	57940	1			T3	833		T7	41		T4	9
valid_sources[0x4c]	55896	1			T3	774		T7	47		T4	11
valid_sources[0x4d]	53357	1			T1	3		T3	833		T7	52
valid_sources[0x4e]	70108	1			T3	818		T7	62		T4	11
valid_sources[0x4f]	59006	1			T2	4		T3	774		T7	58
valid_sources[0x50]	67356	1			T3	760		T7	35		T4	24
valid_sources[0x51]	73047	1			T3	813		T7	44		T4	8
valid_sources[0x52]	59718	1			T3	825		T7	59		T4	10
valid_sources[0x53]	56578	1			T3	784		T7	44		T4	5
valid_sources[0x54]	59398	1			T3	766		T7	52		T4	20
valid_sources[0x55]	53856	1			T1	3		T3	805		T7	34
valid_sources[0x56]	65414	1			T2	5		T3	797		T7	33
valid_sources[0x57]	74521	1			T3	821		T7	43		T4	10
valid_sources[0x58]	55545	1			T3	808		T7	59		T4	6
valid_sources[0x59]	61506	1			T3	802		T7	47		T4	13
valid_sources[0x5a]	53604	1			T3	778		T7	57		T4	14
valid_sources[0x5b]	52756	1			T3	766		T7	46		T4	13
valid_sources[0x5c]	59826	1			T3	814		T7	54		T4	24
valid_sources[0x5d]	103314	1			T1	5		T3	845		T7	50
valid_sources[0x5e]	59481	1			T2	6		T3	869		T7	45
valid_sources[0x5f]	57338	1			T2	2		T3	868		T7	40
valid_sources[0x60]	56151	1			T3	816		T7	44		T4	23
valid_sources[0x61]	53659	1			T3	762		T7	34		T4	13
valid_sources[0x62]	56802	1			T3	825		T7	40		T4	13
valid_sources[0x63]	66998	1			T3	838		T7	39		T4	17
valid_sources[0x64]	55651	1			T1	2		T3	785		T7	46
valid_sources[0x65]	60507	1			T3	800		T7	56		T4	15
valid_sources[0x66]	62952	1			T3	803		T7	58		T4	22
valid_sources[0x67]	55881	1			T3	808		T7	63		T4	7
valid_sources[0x68]	55573	1			T3	776		T7	61		T4	15
valid_sources[0x69]	59300	1			T3	876		T7	71		T4	15
valid_sources[0x6a]	55086	1			T1	4		T3	822		T7	47
valid_sources[0x6b]	62748	1			T1	5		T3	773		T7	63
valid_sources[0x6c]	78650	1			T3	788		T7	75		T4	13
valid_sources[0x6d]	56928	1			T3	816		T7	42		T4	7
valid_sources[0x6e]	62053	1			T3	869		T7	57		T4	18
valid_sources[0x6f]	56550	1			T3	822		T7	40		T4	10
valid_sources[0x70]	54096	1			T3	784		T7	44		T4	13
valid_sources[0x71]	90022	1			T3	775		T7	55		T4	21
valid_sources[0x72]	59467	1			T3	830		T7	51		T4	10
valid_sources[0x73]	61266	1			T3	758		T7	65		T4	17
valid_sources[0x74]	53440	1			T3	821		T7	51		T4	21
valid_sources[0x75]	56549	1			T3	754		T7	64		T4	12
valid_sources[0x76]	59786	1			T3	815		T7	51		T4	13
valid_sources[0x77]	64866	1			T3	794		T7	47		T4	20
valid_sources[0x78]	55034	1			T3	817		T7	36		T4	28
valid_sources[0x79]	59212	1			T3	798		T7	51		T4	13
valid_sources[0x7a]	54891	1			T3	833		T7	42		T4	9
valid_sources[0x7b]	56890	1			T3	782		T7	49		T4	13
valid_sources[0x7c]	61119	1			T3	800		T7	36		T4	17
valid_sources[0x7d]	55504	1			T3	807		T7	47		T4	9
valid_sources[0x7e]	131900	1			T3	794		T7	72		T4	17
valid_sources[0x7f]	57663	1			T3	815		T7	41		T4	13
valid_sources[0x80]	59215	1			T3	769		T7	57		T4	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3674485

1

T1

1

T3

40284

T6

125

values[0x0]

all_enables

biggest_size

2079994

1

T1

21

T2

14

T3

40530

values[0x1]

all_enables

biggest_size

1996652

1

T1

12

T2

8

T3

40149

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	273044	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9792562

1

T3

214696

T6

20

T7

220

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2502842	1			T3	54068		T6	10		T7	110
values[0x0]	3670216	1			T3	80664		T6	7		T7	59
values[0x1]	3892548	1			T3	85467		T6	3		T7	51

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	98732	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9966874

1

T3

218327

T6

20

T7

220

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	40403	1			T3	711		T7	1		T28	1
valid_sources[0x01]	39877	1			T3	1102		T7	1		T5	2
valid_sources[0x02]	39414	1			T3	1097		T7	3		T4	1
valid_sources[0x03]	38066	1			T3	901		T9	665		T122	1
valid_sources[0x04]	40258	1			T3	897		T5	1		T9	676
valid_sources[0x05]	40459	1			T3	903		T9	626		T13	780
valid_sources[0x06]	38206	1			T3	693		T7	2		T9	539
valid_sources[0x07]	39358	1			T3	690		T7	1		T9	657
valid_sources[0x08]	40072	1			T3	884		T7	1		T5	2
valid_sources[0x09]	38274	1			T3	659		T7	1		T9	594
valid_sources[0x0a]	38098	1			T3	848		T27	1		T9	618
valid_sources[0x0b]	39214	1			T3	813		T28	2		T9	613
valid_sources[0x0c]	38343	1			T3	829		T7	1		T9	591
valid_sources[0x0d]	38272	1			T3	775		T7	1		T5	1
valid_sources[0x0e]	39969	1			T3	858		T7	2		T9	620
valid_sources[0x0f]	38805	1			T3	832		T5	1		T9	652
valid_sources[0x10]	39347	1			T3	593		T12	20		T9	568
valid_sources[0x11]	39924	1			T3	871		T7	4		T27	3
valid_sources[0x12]	39482	1			T3	1116		T9	594		T13	795
valid_sources[0x13]	39792	1			T3	909		T27	3		T9	590
valid_sources[0x14]	39921	1			T3	896		T7	1		T5	1
valid_sources[0x15]	38721	1			T3	987		T9	627		T39	1
valid_sources[0x16]	38484	1			T3	849		T9	669		T122	1
valid_sources[0x17]	38917	1			T3	868		T28	4		T9	671
valid_sources[0x18]	38747	1			T3	1029		T4	2		T28	1
valid_sources[0x19]	40253	1			T3	937		T4	2		T5	1
valid_sources[0x1a]	39449	1			T3	1150		T9	618		T122	3
valid_sources[0x1b]	39113	1			T3	1082		T9	642		T99	1
valid_sources[0x1c]	38200	1			T3	1049		T9	627		T93	3
valid_sources[0x1d]	39892	1			T3	902		T9	581		T39	1
valid_sources[0x1e]	39622	1			T3	830		T7	3		T5	1
valid_sources[0x1f]	38592	1			T3	846		T7	3		T9	561
valid_sources[0x20]	39404	1			T3	734		T9	520		T39	1
valid_sources[0x21]	38312	1			T3	842		T7	1		T27	3
valid_sources[0x22]	40422	1			T3	826		T27	1		T9	614
valid_sources[0x23]	38750	1			T3	1101		T7	1		T5	1
valid_sources[0x24]	37816	1			T3	614		T4	2		T28	1
valid_sources[0x25]	39440	1			T3	1029		T9	616		T99	2
valid_sources[0x26]	39241	1			T3	967		T7	1		T9	660
valid_sources[0x27]	38214	1			T3	882		T7	2		T27	2
valid_sources[0x28]	39972	1			T3	803		T7	1		T27	2
valid_sources[0x29]	39175	1			T3	786		T5	1		T9	639
valid_sources[0x2a]	39057	1			T3	818		T5	2		T9	579
valid_sources[0x2b]	40830	1			T3	904		T27	3		T9	622
valid_sources[0x2c]	39291	1			T3	791		T27	3		T9	627
valid_sources[0x2d]	39672	1			T3	872		T7	2		T5	1
valid_sources[0x2e]	38823	1			T3	798		T7	1		T9	686
valid_sources[0x2f]	39070	1			T3	682		T9	682		T39	1
valid_sources[0x30]	38630	1			T3	827		T9	645		T122	1
valid_sources[0x31]	39321	1			T3	975		T9	650		T39	1
valid_sources[0x32]	40251	1			T3	912		T7	1		T9	637
valid_sources[0x33]	38083	1			T3	941		T7	3		T9	581
valid_sources[0x34]	38403	1			T3	727		T7	1		T9	623
valid_sources[0x35]	39120	1			T3	701		T9	687		T95	2
valid_sources[0x36]	38523	1			T3	609		T7	1		T9	556
valid_sources[0x37]	40691	1			T3	991		T7	1		T4	1
valid_sources[0x38]	40030	1			T3	948		T7	3		T9	651
valid_sources[0x39]	39309	1			T3	920		T7	1		T9	651
valid_sources[0x3a]	39594	1			T3	1069		T7	1		T5	2
valid_sources[0x3b]	39172	1			T3	1278		T5	1		T27	1
valid_sources[0x3c]	39064	1			T3	744		T7	5		T5	5
valid_sources[0x3d]	37158	1			T3	616		T7	2		T28	2
valid_sources[0x3e]	40546	1			T3	1248		T7	1		T5	1
valid_sources[0x3f]	40014	1			T3	797		T7	1		T28	3
valid_sources[0x40]	39435	1			T3	667		T5	1		T9	708
valid_sources[0x41]	39414	1			T3	1069		T27	5		T9	632
valid_sources[0x42]	39022	1			T3	815		T7	1		T9	682
valid_sources[0x43]	38201	1			T3	1064		T27	1		T28	1
valid_sources[0x44]	38772	1			T3	901		T7	2		T5	1
valid_sources[0x45]	40112	1			T3	767		T7	1		T9	564
valid_sources[0x46]	40457	1			T3	768		T28	4		T9	688
valid_sources[0x47]	38162	1			T3	803		T7	1		T9	635
valid_sources[0x48]	37655	1			T3	880		T7	1		T5	1
valid_sources[0x49]	40017	1			T3	988		T5	1		T28	2
valid_sources[0x4a]	38558	1			T3	1007		T5	1		T9	694
valid_sources[0x4b]	41402	1			T3	1025		T7	1		T9	651
valid_sources[0x4c]	40115	1			T3	818		T5	1		T27	3
valid_sources[0x4d]	40096	1			T3	788		T5	1		T9	611
valid_sources[0x4e]	39116	1			T3	847		T9	666		T106	1
valid_sources[0x4f]	41289	1			T3	950		T9	610		T122	1
valid_sources[0x50]	38690	1			T3	874		T7	3		T9	716
valid_sources[0x51]	40169	1			T3	780		T9	550		T122	3
valid_sources[0x52]	39427	1			T3	509		T5	2		T28	2
valid_sources[0x53]	39417	1			T3	898		T9	684		T123	1
valid_sources[0x54]	38958	1			T3	938		T7	4		T5	1
valid_sources[0x55]	39691	1			T3	986		T7	1		T4	2
valid_sources[0x56]	39355	1			T3	710		T7	2		T5	1
valid_sources[0x57]	38012	1			T3	722		T7	1		T9	644
valid_sources[0x58]	38312	1			T3	872		T7	2		T4	1
valid_sources[0x59]	37934	1			T3	764		T9	610		T39	1
valid_sources[0x5a]	39801	1			T3	1000		T4	3		T5	2
valid_sources[0x5b]	39159	1			T3	764		T7	1		T9	572
valid_sources[0x5c]	38757	1			T3	874		T9	595		T13	832
valid_sources[0x5d]	39314	1			T3	921		T7	2		T9	657
valid_sources[0x5e]	39193	1			T3	997		T7	1		T9	707
valid_sources[0x5f]	40262	1			T3	574		T9	587		T106	2
valid_sources[0x60]	40062	1			T3	772		T7	1		T27	1
valid_sources[0x61]	40193	1			T3	1127		T7	2		T5	1
valid_sources[0x62]	39221	1			T3	845		T7	3		T4	2
valid_sources[0x63]	39381	1			T3	630		T27	2		T9	604
valid_sources[0x64]	38469	1			T3	766		T9	622		T39	1
valid_sources[0x65]	38694	1			T3	951		T7	4		T5	1
valid_sources[0x66]	39707	1			T3	861		T27	1		T9	587
valid_sources[0x67]	39047	1			T3	1040		T7	2		T5	1
valid_sources[0x68]	38477	1			T3	905		T7	1		T9	679
valid_sources[0x69]	38694	1			T3	798		T9	596		T94	1
valid_sources[0x6a]	38959	1			T3	759		T9	623		T122	2
valid_sources[0x6b]	39710	1			T3	794		T7	1		T28	1
valid_sources[0x6c]	39545	1			T3	954		T7	2		T5	1
valid_sources[0x6d]	40830	1			T3	1003		T7	1		T28	1
valid_sources[0x6e]	39392	1			T3	728		T4	5		T5	1
valid_sources[0x6f]	40378	1			T3	1086		T7	1		T28	2
valid_sources[0x70]	40122	1			T3	837		T5	5		T9	551
valid_sources[0x71]	40842	1			T3	974		T7	1		T5	1
valid_sources[0x72]	38683	1			T3	865		T9	651		T39	1
valid_sources[0x73]	41658	1			T3	1090		T7	3		T9	532
valid_sources[0x74]	37822	1			T3	1178		T5	3		T28	10
valid_sources[0x75]	39424	1			T3	642		T7	3		T5	1
valid_sources[0x76]	38662	1			T3	762		T28	2		T9	617
valid_sources[0x77]	40296	1			T3	715		T5	3		T9	640
valid_sources[0x78]	39326	1			T3	708		T28	2		T9	580
valid_sources[0x79]	39095	1			T3	987		T7	1		T5	1
valid_sources[0x7a]	40096	1			T3	715		T27	10		T9	574
valid_sources[0x7b]	39298	1			T3	774		T7	1		T9	610
valid_sources[0x7c]	39228	1			T3	816		T7	6		T9	651
valid_sources[0x7d]	38758	1			T3	879		T7	1		T9	608
valid_sources[0x7e]	39563	1			T3	1155		T9	587		T92	3
valid_sources[0x7f]	37737	1			T3	898		T27	2		T9	670
valid_sources[0x80]	38209	1			T3	742		T4	2		T27	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2487597

1

T3

54035

T6

10

T7

110

values[0x0]

all_enables

biggest_size

3651464

1

T3

80305

T6

7

T7

59

values[0x1]

all_enables

biggest_size

3653501

1

T3

80356

T6

3

T7

51