Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

27576772

1

T1

75

T2

44

T3

512644

full_word

8939458

1

T1

34

T2

22

T3

146955

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	36515910	1			T1	109		T2	66		T3	659599
auto[TlIntgErrCmd]	113	1			T266	8		T267	8		T268	8
auto[TlIntgErrData]	100	1			T266	6		T267	4		T268	5
auto[TlIntgErrBoth]	107	1			T266	6		T267	8		T268	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10500353

1

T1

1

T2

1

T3

111631

auto[1]

26015877

1

T1

108

T2

65

T3

547968

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6681252	1			T2	1		T3	68092		T6	376
auto[TlIntgErrNone]	partial	auto[1]	20895226	1			T1	75		T2	43		T3	444552
auto[TlIntgErrNone]	full_word	auto[0]	3818950	1			T1	1		T3	43539		T6	125
auto[TlIntgErrNone]	full_word	auto[1]	5120482	1			T1	33		T2	22		T3	103416
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T266	3		T267	3		T268	2
auto[TlIntgErrCmd]	partial	auto[1]	71	1			T266	5		T267	4		T268	6
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T267	1		T368	1		T370	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T371	1		T372	1		-	-
auto[TlIntgErrData]	partial	auto[0]	53	1			T266	1		T267	1		T268	2
auto[TlIntgErrData]	partial	auto[1]	38	1			T266	5		T267	3		T268	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T364	2		T373	1		T374	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T371	1		T369	2		T366	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T266	3		T267	1		T268	4
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T266	3		T267	6		T268	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T267	1		T268	1		T375	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T371	1		T376	1		T369	1