Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.16	94.16	96.15	96.90		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	525631732	8848435	0	0
check_regwen_rd_A	525631732	3319	0	0
check_timeout_rd_A	525631732	2341	0	0
check_trigger_regwen_rd_A	525631732	3533	0	0
consistency_check_period_rd_A	525631732	3579	0	0
creator_sw_cfg_read_lock_rd_A	525631732	2393	0	0
direct_access_address_rd_A	525631732	2345	0	0
direct_access_wdata_0_rd_A	525631732	1557	0	0
direct_access_wdata_1_rd_A	525631732	1866	0	0
integrity_check_period_rd_A	525631732	3438	0	0
intr_enable_rd_A	525631732	4450	0	0
owner_sw_cfg_read_lock_rd_A	525631732	2043	0	0
rot_creator_auth_codesign_read_lock_rd_A	525631732	2383	0	0
rot_creator_auth_state_read_lock_rd_A	525631732	2223	0	0
vendor_test_read_lock_rd_A	525631732	2094	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525631732	8848435	0	0
T3	913529	191153	0	0
T4	39786	0	0	0
T5	114787	0	0	0
T6	12565	0	0	0
T7	32157	0	0	0
T9	0	139534	0	0
T10	11506	0	0	0
T11	13890	0	0	0
T12	13106	0	0	0
T13	0	185605	0	0
T16	0	201892	0	0
T17	0	40056	0	0
T18	0	103150	0	0
T27	47511	0	0	0
T28	116418	0	0	0
T37	0	52101	0	0
T132	0	86242	0	0
T256	0	31516	0	0
T272	0	69706	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525631732	3319	0	0
T16	144138	177	0	0
T67	195072	0	0	0
T97	61493	0	0	0
T100	32898	0	0	0
T110	10271	0	0	0
T132	0	73	0	0
T160	16971	0	0	0
T164	11926	0	0	0
T203	11247	0	0	0
T221	17558	0	0	0
T222	14360	0	0	0
T256	0	20	0	0
T275	0	69	0	0
T284	0	92	0	0
T285	0	121	0	0
T341	0	156	0	0
T346	0	76	0	0
T347	0	86	0	0
T348	0	98	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525631732	2341	0	0
T16	144138	263	0	0
T67	195072	0	0	0
T97	61493	0	0	0
T100	32898	0	0	0
T110	10271	0	0	0
T132	0	107	0	0
T160	16971	0	0	0
T164	11926	0	0	0
T203	11247	0	0	0
T221	17558	0	0	0
T222	14360	0	0	0
T256	0	35	0	0
T275	0	136	0	0
T284	0	108	0	0
T285	0	66	0	0
T341	0	130	0	0
T346	0	69	0	0
T347	0	65	0	0
T348	0	122	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525631732	3533	0	0
T16	144138	300	0	0
T67	195072	0	0	0
T97	61493	0	0	0
T100	32898	0	0	0
T110	10271	0	0	0
T132	0	116	0	0
T160	16971	0	0	0
T164	11926	0	0	0
T203	11247	0	0	0
T221	17558	0	0	0
T222	14360	0	0	0
T256	0	28	0	0
T275	0	114	0	0
T284	0	97	0	0
T285	0	114	0	0
T341	0	130	0	0
T346	0	47	0	0
T347	0	56	0	0
T348	0	117	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525631732	3579	0	0
T16	144138	279	0	0
T67	195072	0	0	0
T97	61493	0	0	0
T100	32898	0	0	0
T110	10271	0	0	0
T132	0	85	0	0
T160	16971	0	0	0
T164	11926	0	0	0
T203	11247	0	0	0
T221	17558	0	0	0
T222	14360	0	0	0
T256	0	18	0	0
T275	0	151	0	0
T284	0	133	0	0
T285	0	80	0	0
T341	0	123	0	0
T346	0	48	0	0
T347	0	97	0	0
T348	0	62	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525631732	2393	0	0
T16	144138	259	0	0
T67	195072	0	0	0
T97	61493	0	0	0
T100	32898	0	0	0
T110	10271	0	0	0
T132	0	145	0	0
T160	16971	0	0	0
T164	11926	0	0	0
T203	11247	0	0	0
T221	17558	0	0	0
T222	14360	0	0	0
T256	0	20	0	0
T275	0	126	0	0
T284	0	89	0	0
T285	0	97	0	0
T341	0	133	0	0
T346	0	65	0	0
T347	0	96	0	0
T348	0	121	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525631732	2345	0	0
T16	144138	303	0	0
T67	195072	0	0	0
T97	61493	0	0	0
T100	32898	0	0	0
T110	10271	0	0	0
T132	0	111	0	0
T160	16971	0	0	0
T164	11926	0	0	0
T203	11247	0	0	0
T221	17558	0	0	0
T222	14360	0	0	0
T256	0	33	0	0
T275	0	130	0	0
T284	0	68	0	0
T285	0	93	0	0
T341	0	141	0	0
T346	0	85	0	0
T347	0	86	0	0
T348	0	116	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525631732	1557	0	0
T16	144138	183	0	0
T67	195072	0	0	0
T97	61493	0	0	0
T100	32898	0	0	0
T110	10271	0	0	0
T132	0	87	0	0
T160	16971	0	0	0
T164	11926	0	0	0
T203	11247	0	0	0
T221	17558	0	0	0
T222	14360	0	0	0
T256	0	6	0	0
T275	0	53	0	0
T284	0	74	0	0
T285	0	59	0	0
T341	0	106	0	0
T346	0	46	0	0
T347	0	47	0	0
T348	0	26	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525631732	1866	0	0
T16	144138	181	0	0
T67	195072	0	0	0
T97	61493	0	0	0
T100	32898	0	0	0
T110	10271	0	0	0
T132	0	122	0	0
T160	16971	0	0	0
T164	11926	0	0	0
T203	11247	0	0	0
T221	17558	0	0	0
T222	14360	0	0	0
T256	0	13	0	0
T275	0	75	0	0
T284	0	100	0	0
T285	0	71	0	0
T341	0	177	0	0
T346	0	78	0	0
T347	0	61	0	0
T348	0	83	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525631732	3438	0	0
T16	144138	181	0	0
T67	195072	0	0	0
T97	61493	0	0	0
T100	32898	0	0	0
T110	10271	0	0	0
T132	0	95	0	0
T160	16971	0	0	0
T164	11926	0	0	0
T203	11247	0	0	0
T221	17558	0	0	0
T222	14360	0	0	0
T256	0	15	0	0
T275	0	88	0	0
T284	0	93	0	0
T285	0	85	0	0
T341	0	133	0	0
T346	0	40	0	0
T347	0	77	0	0
T348	0	76	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525631732	4450	0	0
T16	144138	245	0	0
T67	195072	0	0	0
T97	61493	0	0	0
T100	32898	0	0	0
T110	10271	0	0	0
T113	0	62	0	0
T132	0	127	0	0
T160	16971	0	0	0
T164	11926	0	0	0
T203	11247	0	0	0
T221	17558	0	0	0
T222	14360	0	0	0
T253	0	12	0	0
T256	0	23	0	0
T275	0	103	0	0
T341	0	144	0	0
T346	0	87	0	0
T347	0	63	0	0
T349	0	78	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525631732	2043	0	0
T16	144138	178	0	0
T67	195072	0	0	0
T97	61493	0	0	0
T100	32898	0	0	0
T110	10271	0	0	0
T132	0	88	0	0
T160	16971	0	0	0
T164	11926	0	0	0
T203	11247	0	0	0
T221	17558	0	0	0
T222	14360	0	0	0
T256	0	30	0	0
T275	0	96	0	0
T284	0	82	0	0
T285	0	75	0	0
T341	0	153	0	0
T346	0	79	0	0
T347	0	65	0	0
T348	0	102	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525631732	2383	0	0
T16	144138	249	0	0
T67	195072	0	0	0
T97	61493	0	0	0
T100	32898	0	0	0
T110	10271	0	0	0
T132	0	108	0	0
T160	16971	0	0	0
T164	11926	0	0	0
T203	11247	0	0	0
T221	17558	0	0	0
T222	14360	0	0	0
T256	0	16	0	0
T275	0	115	0	0
T284	0	78	0	0
T285	0	60	0	0
T341	0	191	0	0
T346	0	56	0	0
T347	0	70	0	0
T348	0	104	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525631732	2223	0	0
T16	144138	218	0	0
T67	195072	0	0	0
T97	61493	0	0	0
T100	32898	0	0	0
T110	10271	0	0	0
T132	0	131	0	0
T160	16971	0	0	0
T164	11926	0	0	0
T203	11247	0	0	0
T221	17558	0	0	0
T222	14360	0	0	0
T256	0	31	0	0
T275	0	96	0	0
T284	0	79	0	0
T285	0	57	0	0
T341	0	140	0	0
T346	0	81	0	0
T347	0	83	0	0
T348	0	96	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525631732	2094	0	0
T16	144138	213	0	0
T67	195072	0	0	0
T97	61493	0	0	0
T100	32898	0	0	0
T110	10271	0	0	0
T132	0	92	0	0
T160	16971	0	0	0
T164	11926	0	0	0
T203	11247	0	0	0
T221	17558	0	0	0
T222	14360	0	0	0
T256	0	2	0	0
T275	0	75	0	0
T284	0	108	0	0
T285	0	108	0	0
T341	0	112	0	0
T346	0	38	0	0
T347	0	62	0	0
T348	0	100	0	0