Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.16	94.16	96.15	96.90		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.16	94.16	96.15	96.90		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T70,T81,T82

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T4,T27,T38

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T7,T4
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T74,T161
1	Covered	T74,T161

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T7,T4
1	Covered	T3,T7,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T10

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T4
1	1	Covered	T3,T4,T10

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T3,T7,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T3,T4,T10
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T3,T4,T10
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T12,T28

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T12,T28

---

FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T7,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T3,T7,T4
ReadWaitSt	252	Covered	T3,T4,T10
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T7,T4
IdleSt->ReadSt	236	Covered	T3,T7,T4
InitSt->ErrorSt	315	Covered	T10,T164,T188
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T68,T110,T186
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T7,T5
ReadSt->ReadWaitSt	252	Covered	T3,T4,T10
ReadWaitSt->ErrorSt	276	Covered	T153,T210,T154
ReadWaitSt->IdleSt	270	Covered	T3,T4,T10
ResetSt->ErrorSt	315	Covered	T74,T75,T76
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T3,T7,T5
CheckFailError	317	Covered	T74,T161
FsmStateError	289	Covered	T3,T7,T4
MacroEccCorrError	221	Covered	T4,T27,T38
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T3,T7,T8
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T3,T7,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T74,T161
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T7,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T4,T70,T81
MacroEccCorrError->NoError	235	Covered	T4,T27,T38
NoError->AccessError	256	Covered	T3,T7,T5
NoError->CheckFailError	317	Covered	T74,T161
NoError->FsmStateError	289	Covered	T3,T4,T10
NoError->MacroEccCorrError	221	Covered	T4,T27,T38

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T10

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T10

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T12,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T70,T81,T82
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T110,T162,T211
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T7,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T3,T4,T10
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T16,T97,T37
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T7,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T4,T27,T38
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T3,T10,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T153,T210,T154
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T4,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T7,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T7,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T7,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T7,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T74,T161
1	0	Covered	T74,T161
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T7,T4
1	0	Covered	T3,T7,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T7,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	522522042	521645226	0	0
DigestKnown_A	522522042	521645226	0	0
DigestOffsetMustBeRepresentable_A	1153	1153	0	0
EccErrorState_A	522522042	6193	0	0
ErrorKnown_A	522522042	521645226	0	0
FsmStateKnown_A	522522042	521645226	0	0
InitDoneKnown_A	522522042	521645226	0	0
InitReadLocksPartition_A	522522042	92762513	0	0
InitWriteLocksPartition_A	522522042	92762513	0	0
OffsetMustBeBlockAligned_A	1153	1153	0	0
OtpAddrKnown_A	522522042	521645226	0	0
OtpCmdKnown_A	522522042	521645226	0	0
OtpErrorState_A	522522042	37	0	0
OtpReqKnown_A	522522042	521645226	0	0
OtpSizeKnown_A	522522042	521645226	0	0
OtpWdataKnown_A	522522042	521645226	0	0
ReadLockPropagation_A	522522042	247483091	0	0
SizeMustBeBlockAligned_A	1153	1153	0	0
TlulGntKnown_A	522522042	521645226	0	0
TlulRdataKnown_A	522522042	521645226	0	0
TlulReadOnReadLock_A	522522042	8600	0	0
TlulRerrorKnown_A	522522042	521645226	0	0
TlulRvalidKnown_A	522522042	521645226	0	0
WriteLockPropagation_A	522522042	3471457	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	522522042	34357276	0	0
u_state_regs_A	522522042	521645226	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	6193	0	0
T37	238943	0	0	0
T62	150467	0	0	0
T74	14483	2725	0	0
T98	57365	0	0	0
T101	940630	0	0	0
T102	82866	0	0	0
T103	99028	0	0	0
T161	0	3468	0	0
T212	17661	0	0	0
T213	87660	0	0	0
T214	34176	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	92762513	0	0
T1	5442	112	0	0
T2	5585	100	0	0
T3	913529	78158	0	0
T4	39786	18207	0	0
T5	114787	1406	0	0
T6	12565	459	0	0
T7	32157	20981	0	0
T10	11506	4201	0	0
T11	13890	4438	0	0
T12	13106	223	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	92762513	0	0
T1	5442	112	0	0
T2	5585	100	0	0
T3	913529	78158	0	0
T4	39786	18207	0	0
T5	114787	1406	0	0
T6	12565	459	0	0
T7	32157	20981	0	0
T10	11506	4201	0	0
T11	13890	4438	0	0
T12	13106	223	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	37	0	0
T100	32898	0	0	0
T110	10271	1	0	0
T153	0	1	0	0
T160	16971	0	0	0
T162	0	1	0	0
T164	11926	0	0	0
T186	13236	0	0	0
T187	13592	0	0	0
T211	0	1	0	0
T215	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0
T218	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0
T221	17558	0	0	0
T222	14360	0	0	0
T223	20600	0	0	0
T224	98939	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	247483091	0	0
T3	913529	527216	0	0
T4	39786	0	0	0
T5	114787	33354	0	0
T6	12565	0	0	0
T7	32157	23962	0	0
T8	0	11095	0	0
T9	0	202107	0	0
T10	11506	0	0	0
T11	13890	0	0	0
T12	13106	0	0	0
T14	0	19508	0	0
T27	47511	2660	0	0
T28	116418	32294	0	0
T38	0	3241	0	0
T39	0	8978	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	8600	0	0
T3	913529	54	0	0
T4	39786	5	0	0
T5	114787	3	0	0
T6	12565	0	0	0
T7	32157	21	0	0
T8	0	1	0	0
T9	0	35	0	0
T10	11506	0	0	0
T11	13890	0	0	0
T12	13106	0	0	0
T27	47511	8	0	0
T28	116418	8	0	0
T38	0	4	0	0
T39	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	3471457	0	0
T5	114787	31804	0	0
T8	19179	0	0	0
T9	481972	0	0	0
T12	13106	0	0	0
T27	47511	0	0	0
T28	116418	0	0	0
T31	18635	0	0	0
T38	41709	0	0	0
T39	83377	5938	0	0
T53	13346	0	0	0
T62	0	17037	0	0
T67	0	4872	0	0
T93	0	9222	0	0
T96	0	9060	0	0
T101	0	41924	0	0
T105	0	71180	0	0
T118	0	11552	0	0
T225	0	4068	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	34357276	0	0
T5	114787	73138	0	0
T8	19179	0	0	0
T9	481972	0	0	0
T12	13106	4035	0	0
T27	47511	0	0	0
T28	116418	96748	0	0
T31	18635	0	0	0
T38	41709	33597	0	0
T39	83377	71858	0	0
T53	13346	0	0	0
T92	0	41871	0	0
T93	0	59489	0	0
T99	0	4194	0	0
T152	0	2906	0	0
T163	0	3410	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T81,T82,T77

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T7,T10
1	Covered	T4,T27,T38

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T7,T4
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T148
1	Covered	T148

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T3,T7,T4
1	Covered	T3,T7,T4

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T7,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T4
1	1	Covered	T3,T7,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T3,T7,T4

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T3,T7,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T3,T7,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T12,T39

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T12,T39

---

FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T3,T7,T4
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T3,T7,T4
ReadWaitSt	252	Covered	T3,T7,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T3,T7,T4
IdleSt->ReadSt	236	Covered	T3,T7,T4
InitSt->ErrorSt	315	Covered	T10,T68,T164
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T69,T203,T110
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T7,T5
ReadSt->ReadWaitSt	252	Covered	T3,T7,T4
ReadWaitSt->ErrorSt	276	Covered	T165,T167,T226
ReadWaitSt->IdleSt	270	Covered	T3,T7,T4
ResetSt->ErrorSt	315	Covered	T74,T75,T76
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T3,T7,T5
CheckFailError	317	Covered	T148
FsmStateError	289	Covered	T3,T7,T4
MacroEccCorrError	221	Covered	T4,T27,T38
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T3,T7,T8
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T3,T7,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T148
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T3,T7,T4
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T4,T81,T159
MacroEccCorrError->NoError	235	Covered	T27,T38,T67
NoError->AccessError	256	Covered	T3,T7,T5
NoError->CheckFailError	317	Covered	T148
NoError->FsmStateError	289	Covered	T3,T4,T10
NoError->MacroEccCorrError	221	Covered	T4,T27,T38

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T12,T39
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T81,T82,T77
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T69,T203,T227
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T7,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T3,T7,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T94,T16,T97
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T7,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T4,T27,T38
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T3,T7,T10
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T165,T167,T226
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T7,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T3,T7,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T7,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T3,T7,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T3,T7,T4
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T148
1	0	Covered	T148
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T3,T7,T4
1	0	Covered	T3,T7,T4
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T7,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	522522042	521645226	0	0
DigestKnown_A	522522042	521645226	0	0
DigestOffsetMustBeRepresentable_A	1153	1153	0	0
EccErrorState_A	522522042	2828	0	0
ErrorKnown_A	522522042	521645226	0	0
FsmStateKnown_A	522522042	521645226	0	0
InitDoneKnown_A	522522042	521645226	0	0
InitReadLocksPartition_A	522522042	92945258	0	0
InitWriteLocksPartition_A	522522042	92945258	0	0
OffsetMustBeBlockAligned_A	1153	1153	0	0
OtpAddrKnown_A	522522042	521645226	0	0
OtpCmdKnown_A	522522042	521645226	0	0
OtpErrorState_A	522522042	40	0	0
OtpReqKnown_A	522522042	521645226	0	0
OtpSizeKnown_A	522522042	521645226	0	0
OtpWdataKnown_A	522522042	521645226	0	0
ReadLockPropagation_A	522522042	244085680	0	0
SizeMustBeBlockAligned_A	1153	1153	0	0
TlulGntKnown_A	522522042	521645226	0	0
TlulRdataKnown_A	522522042	521645226	0	0
TlulReadOnReadLock_A	522522042	8458	0	0
TlulRerrorKnown_A	522522042	521645226	0	0
TlulRvalidKnown_A	522522042	521645226	0	0
WriteLockPropagation_A	522522042	1604119	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	522522042	18744638	0	0
u_state_regs_A	522522042	521645226	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	2828	0	0
T148	13824	2828	0	0
T168	59708	0	0	0
T169	10993	0	0	0
T170	17846	0	0	0
T171	87408	0	0	0
T172	7252	0	0	0
T173	24981	0	0	0
T174	80340	0	0	0
T175	69705	0	0	0
T176	11670	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	92945258	0	0
T1	5442	129	0	0
T2	5585	117	0	0
T3	913529	78413	0	0
T4	39786	18309	0	0
T5	114787	1559	0	0
T6	12565	510	0	0
T7	32157	21032	0	0
T10	11506	4218	0	0
T11	13890	4472	0	0
T12	13106	257	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	92945258	0	0
T1	5442	129	0	0
T2	5585	117	0	0
T3	913529	78413	0	0
T4	39786	18309	0	0
T5	114787	1559	0	0
T6	12565	510	0	0
T7	32157	21032	0	0
T10	11506	4218	0	0
T11	13890	4472	0	0
T12	13106	257	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	40	0	0
T13	861681	0	0	0
T69	13627	1	0	0
T70	10611	0	0	0
T81	9147	0	0	0
T94	80623	0	0	0
T95	35626	0	0	0
T108	10033	0	0	0
T157	11385	0	0	0
T158	76163	0	0	0
T163	25161	0	0	0
T165	0	1	0	0
T167	0	1	0	0
T203	0	1	0	0
T226	0	1	0	0
T227	0	1	0	0
T228	0	1	0	0
T229	0	1	0	0
T230	0	1	0	0
T231	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	244085680	0	0
T3	913529	584257	0	0
T4	39786	0	0	0
T5	114787	28802	0	0
T6	12565	0	0	0
T7	32157	23069	0	0
T8	0	11093	0	0
T9	0	200222	0	0
T10	11506	0	0	0
T11	13890	0	0	0
T12	13106	0	0	0
T14	0	19506	0	0
T27	47511	5717	0	0
T28	116418	21378	0	0
T38	0	4993	0	0
T39	0	8872	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153	1153	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	8458	0	0
T3	913529	61	0	0
T4	39786	7	0	0
T5	114787	4	0	0
T6	12565	0	0	0
T7	32157	32	0	0
T8	0	6	0	0
T9	0	33	0	0
T10	11506	0	0	0
T11	13890	0	0	0
T12	13106	0	0	0
T27	47511	16	0	0
T28	116418	2	0	0
T38	0	5	0	0
T39	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	1604119	0	0
T5	114787	13928	0	0
T8	19179	0	0	0
T9	481972	0	0	0
T12	13106	0	0	0
T27	47511	0	0	0
T28	116418	0	0	0
T31	18635	0	0	0
T38	41709	0	0	0
T39	83377	6609	0	0
T53	13346	0	0	0
T93	0	4633	0	0
T96	0	25417	0	0
T97	0	5149	0	0
T100	0	3534	0	0
T101	0	17777	0	0
T118	0	11015	0	0
T232	0	8544	0	0
T233	0	11802	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	18744638	0	0
T5	114787	95092	0	0
T8	19179	0	0	0
T9	481972	0	0	0
T12	13106	4018	0	0
T27	47511	0	0	0
T28	116418	0	0	0
T31	18635	0	0	0
T38	41709	0	0	0
T39	83377	71705	0	0
T53	13346	0	0	0
T69	0	2718	0	0
T93	0	59302	0	0
T96	0	82326	0	0
T97	0	48762	0	0
T100	0	24517	0	0
T101	0	138172	0	0
T203	0	3526	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522522042	521645226	0	0
T1	5442	5387	0	0
T2	5585	5521	0	0
T3	913529	913466	0	0
T4	39786	39428	0	0
T5	114787	113997	0	0
T6	12565	12296	0	0
T7	32157	31915	0	0
T10	11506	11312	0	0
T11	13890	13568	0	0
T12	13106	12884	0	0