Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

28330994

1

T1

1016

T2

476

T3

1934

full_word

9097132

1

T1

256

T2

218

T3

640

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	37427836	1			T1	1272		T2	694		T3	2574
auto[TlIntgErrCmd]	96	1			T272	5		T273	8		T274	4
auto[TlIntgErrData]	101	1			T272	9		T273	7		T274	5
auto[TlIntgErrBoth]	93	1			T272	6		T273	5		T274	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9872137

1

T1

964

T2

456

T3

2392

auto[1]

27555989

1

T1

308

T2

238

T3

182

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6163482	1			T1	820		T2	341		T3	1829
auto[TlIntgErrNone]	partial	auto[1]	22167253	1			T1	196		T2	135		T3	105
auto[TlIntgErrNone]	full_word	auto[0]	3708524	1			T1	144		T2	115		T3	563
auto[TlIntgErrNone]	full_word	auto[1]	5388577	1			T1	112		T2	103		T3	77
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T272	2		T273	6		T274	1
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T272	3		T273	2		T274	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T370	2		T373	1		T374	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T274	1		T368	1		T367	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T272	5		T273	2		T274	2
auto[TlIntgErrData]	partial	auto[1]	47	1			T272	3		T273	4		T274	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T272	1		T273	1		T368	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T371	1		T375	1		T277	2
auto[TlIntgErrBoth]	partial	auto[0]	30	1			T272	2		T273	1		T274	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T272	2		T273	3		T369	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T273	1		T368	1		T376	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T272	2		T276	1		T371	2