Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.24	94.16	96.15	97.26		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	540008417	9424192	0	0
check_regwen_rd_A	540008417	3947	0	0
check_timeout_rd_A	540008417	2826	0	0
check_trigger_regwen_rd_A	540008417	4112	0	0
consistency_check_period_rd_A	540008417	4186	0	0
creator_sw_cfg_read_lock_rd_A	540008417	2999	0	0
direct_access_address_rd_A	540008417	2095	0	0
direct_access_wdata_0_rd_A	540008417	1463	0	0
direct_access_wdata_1_rd_A	540008417	1539	0	0
integrity_check_period_rd_A	540008417	4244	0	0
intr_enable_rd_A	540008417	4911	0	0
owner_sw_cfg_read_lock_rd_A	540008417	2743	0	0
rot_creator_auth_codesign_read_lock_rd_A	540008417	2840	0	0
rot_creator_auth_state_read_lock_rd_A	540008417	2680	0	0
vendor_test_read_lock_rd_A	540008417	2958	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540008417	9424192	0	0
T7	310449	61800	0	0
T8	258851	55067	0	0
T9	595571	126124	0	0
T18	208405	0	0	0
T19	0	39300	0	0
T20	0	34768	0	0
T21	0	46610	0	0
T38	0	53537	0	0
T56	0	153503	0	0
T70	65095	0	0	0
T71	13771	0	0	0
T100	11753	0	0	0
T101	13969	0	0	0
T102	646577	0	0	0
T105	19716	0	0	0
T129	0	28080	0	0
T278	0	183204	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540008417	3947	0	0
T7	310449	40	0	0
T8	258851	0	0	0
T9	595571	0	0	0
T18	208405	0	0	0
T20	0	62	0	0
T70	65095	0	0	0
T71	13771	0	0	0
T100	11753	0	0	0
T101	13969	0	0	0
T102	646577	0	0	0
T105	19716	0	0	0
T129	0	30	0	0
T226	0	27	0	0
T283	0	39	0	0
T287	0	23	0	0
T288	0	62	0	0
T353	0	100	0	0
T354	0	11	0	0
T355	0	74	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540008417	2826	0	0
T7	310449	61	0	0
T8	258851	0	0	0
T9	595571	0	0	0
T18	208405	0	0	0
T20	0	69	0	0
T70	65095	0	0	0
T71	13771	0	0	0
T100	11753	0	0	0
T101	13969	0	0	0
T102	646577	0	0	0
T105	19716	0	0	0
T129	0	32	0	0
T226	0	40	0	0
T283	0	54	0	0
T287	0	88	0	0
T288	0	121	0	0
T353	0	104	0	0
T354	0	21	0	0
T355	0	88	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540008417	4112	0	0
T7	310449	31	0	0
T8	258851	0	0	0
T9	595571	0	0	0
T18	208405	0	0	0
T20	0	39	0	0
T70	65095	0	0	0
T71	13771	0	0	0
T100	11753	0	0	0
T101	13969	0	0	0
T102	646577	0	0	0
T105	19716	0	0	0
T129	0	76	0	0
T226	0	43	0	0
T283	0	38	0	0
T287	0	72	0	0
T288	0	85	0	0
T353	0	117	0	0
T354	0	30	0	0
T355	0	157	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540008417	4186	0	0
T7	310449	25	0	0
T8	258851	0	0	0
T9	595571	0	0	0
T18	208405	0	0	0
T20	0	74	0	0
T70	65095	0	0	0
T71	13771	0	0	0
T100	11753	0	0	0
T101	13969	0	0	0
T102	646577	0	0	0
T105	19716	0	0	0
T129	0	51	0	0
T226	0	39	0	0
T283	0	53	0	0
T287	0	53	0	0
T288	0	44	0	0
T353	0	115	0	0
T354	0	52	0	0
T355	0	148	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540008417	2999	0	0
T7	310449	73	0	0
T8	258851	0	0	0
T9	595571	0	0	0
T18	208405	0	0	0
T20	0	78	0	0
T70	65095	0	0	0
T71	13771	0	0	0
T100	11753	0	0	0
T101	13969	0	0	0
T102	646577	0	0	0
T105	19716	0	0	0
T129	0	61	0	0
T226	0	63	0	0
T283	0	54	0	0
T287	0	66	0	0
T288	0	70	0	0
T353	0	144	0	0
T354	0	30	0	0
T355	0	104	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540008417	2095	0	0
T7	310449	40	0	0
T8	258851	0	0	0
T9	595571	0	0	0
T18	208405	0	0	0
T20	0	70	0	0
T70	65095	0	0	0
T71	13771	0	0	0
T100	11753	0	0	0
T101	13969	0	0	0
T102	646577	0	0	0
T105	19716	0	0	0
T129	0	56	0	0
T226	0	68	0	0
T283	0	33	0	0
T287	0	73	0	0
T288	0	75	0	0
T353	0	174	0	0
T354	0	38	0	0
T355	0	96	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540008417	1463	0	0
T7	310449	30	0	0
T8	258851	0	0	0
T9	595571	0	0	0
T18	208405	0	0	0
T20	0	11	0	0
T70	65095	0	0	0
T71	13771	0	0	0
T100	11753	0	0	0
T101	13969	0	0	0
T102	646577	0	0	0
T105	19716	0	0	0
T129	0	18	0	0
T226	0	22	0	0
T283	0	41	0	0
T287	0	31	0	0
T288	0	72	0	0
T353	0	96	0	0
T354	0	21	0	0
T355	0	56	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540008417	1539	0	0
T7	310449	46	0	0
T8	258851	0	0	0
T9	595571	0	0	0
T18	208405	0	0	0
T20	0	51	0	0
T70	65095	0	0	0
T71	13771	0	0	0
T100	11753	0	0	0
T101	13969	0	0	0
T102	646577	0	0	0
T105	19716	0	0	0
T129	0	20	0	0
T226	0	30	0	0
T283	0	50	0	0
T287	0	27	0	0
T288	0	63	0	0
T353	0	84	0	0
T354	0	28	0	0
T355	0	78	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540008417	4244	0	0
T7	310449	34	0	0
T8	258851	0	0	0
T9	595571	0	0	0
T18	208405	0	0	0
T20	0	66	0	0
T70	65095	0	0	0
T71	13771	0	0	0
T100	11753	0	0	0
T101	13969	0	0	0
T102	646577	0	0	0
T105	19716	0	0	0
T129	0	40	0	0
T226	0	70	0	0
T283	0	45	0	0
T287	0	49	0	0
T288	0	94	0	0
T353	0	110	0	0
T354	0	41	0	0
T355	0	110	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540008417	4911	0	0
T7	310449	42	0	0
T8	258851	0	0	0
T9	595571	0	0	0
T18	208405	0	0	0
T20	0	71	0	0
T70	65095	0	0	0
T71	13771	0	0	0
T76	0	7	0	0
T100	11753	0	0	0
T101	13969	0	0	0
T102	646577	0	0	0
T105	19716	0	0	0
T129	0	27	0	0
T226	0	131	0	0
T283	0	63	0	0
T287	0	41	0	0
T353	0	178	0	0
T354	0	17	0	0
T355	0	86	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540008417	2743	0	0
T7	310449	61	0	0
T8	258851	0	0	0
T9	595571	0	0	0
T18	208405	0	0	0
T20	0	38	0	0
T70	65095	0	0	0
T71	13771	0	0	0
T100	11753	0	0	0
T101	13969	0	0	0
T102	646577	0	0	0
T105	19716	0	0	0
T129	0	72	0	0
T226	0	60	0	0
T283	0	84	0	0
T287	0	53	0	0
T288	0	95	0	0
T353	0	118	0	0
T354	0	12	0	0
T355	0	129	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540008417	2840	0	0
T7	310449	67	0	0
T8	258851	0	0	0
T9	595571	0	0	0
T18	208405	0	0	0
T20	0	80	0	0
T70	65095	0	0	0
T71	13771	0	0	0
T100	11753	0	0	0
T101	13969	0	0	0
T102	646577	0	0	0
T105	19716	0	0	0
T129	0	76	0	0
T226	0	59	0	0
T283	0	42	0	0
T287	0	74	0	0
T288	0	65	0	0
T353	0	117	0	0
T354	0	36	0	0
T355	0	108	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540008417	2680	0	0
T7	310449	45	0	0
T8	258851	0	0	0
T9	595571	0	0	0
T18	208405	0	0	0
T20	0	45	0	0
T70	65095	0	0	0
T71	13771	0	0	0
T100	11753	0	0	0
T101	13969	0	0	0
T102	646577	0	0	0
T105	19716	0	0	0
T129	0	54	0	0
T226	0	33	0	0
T283	0	40	0	0
T287	0	74	0	0
T288	0	100	0	0
T353	0	161	0	0
T354	0	35	0	0
T355	0	78	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540008417	2958	0	0
T7	310449	55	0	0
T8	258851	0	0	0
T9	595571	0	0	0
T18	208405	0	0	0
T20	0	62	0	0
T70	65095	0	0	0
T71	13771	0	0	0
T100	11753	0	0	0
T101	13969	0	0	0
T102	646577	0	0	0
T105	19716	0	0	0
T129	0	40	0	0
T226	0	49	0	0
T283	0	48	0	0
T287	0	52	0	0
T288	0	64	0	0
T353	0	199	0	0
T354	0	42	0	0
T355	0	107	0	0