Line Coverage for Module :
prim_sync_reqack_data
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 0 | 0 | |
CONT_ASSIGN | 156 | 0 | 0 | |
ALWAYS | 159 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
93 |
1 |
1 |
153 |
|
unreachable |
156 |
|
unreachable |
159 |
|
unreachable |
160 |
|
unreachable |
162 |
|
unreachable |
Assert Coverage for Module :
prim_sync_reqack_data
Assertion Details
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
536742316 |
537392 |
0 |
0 |
T4 |
24778 |
192 |
0 |
0 |
T5 |
23882 |
497 |
0 |
0 |
T6 |
65095 |
270 |
0 |
0 |
T7 |
310449 |
6520 |
0 |
0 |
T8 |
0 |
612 |
0 |
0 |
T9 |
0 |
544 |
0 |
0 |
T11 |
8269 |
0 |
0 |
0 |
T12 |
10540 |
0 |
0 |
0 |
T13 |
74607 |
826 |
0 |
0 |
T18 |
0 |
264 |
0 |
0 |
T52 |
10824 |
0 |
0 |
0 |
T70 |
0 |
646 |
0 |
0 |
T71 |
13771 |
0 |
0 |
0 |
T100 |
11753 |
0 |
0 |
0 |
T105 |
0 |
184 |
0 |
0 |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
536742316 |
537333 |
0 |
0 |
T4 |
24778 |
192 |
0 |
0 |
T5 |
23882 |
497 |
0 |
0 |
T6 |
65095 |
269 |
0 |
0 |
T7 |
310449 |
6520 |
0 |
0 |
T8 |
0 |
612 |
0 |
0 |
T9 |
0 |
544 |
0 |
0 |
T11 |
8269 |
0 |
0 |
0 |
T12 |
10540 |
0 |
0 |
0 |
T13 |
74607 |
826 |
0 |
0 |
T18 |
0 |
264 |
0 |
0 |
T52 |
10824 |
0 |
0 |
0 |
T70 |
0 |
646 |
0 |
0 |
T71 |
13771 |
0 |
0 |
0 |
T100 |
11753 |
0 |
0 |
0 |
T105 |
0 |
184 |
0 |
0 |