Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7182570	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6942542

1

T1

2098

T2

1312

T3

665

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8356706	1			T1	9025		T2	2619		T3	5551
values[0x0]	2206701	1			T1	287		T2	177		T3	177
values[0x1]	3561705	1			T1	291		T2	155		T3	184

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4692163	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9432949

1

T1

4317

T2

1637

T3

2280

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57384	1			T1	29		T5	738		T8	18
valid_sources[0x01]	50215	1			T1	43		T5	704		T8	17
valid_sources[0x02]	48232	1			T1	40		T4	81		T5	775
valid_sources[0x03]	63045	1			T1	45		T5	754		T8	19
valid_sources[0x04]	59243	1			T1	31		T3	88		T5	718
valid_sources[0x05]	51220	1			T1	46		T5	741		T8	23
valid_sources[0x06]	142288	1			T1	38		T5	770		T8	17
valid_sources[0x07]	47920	1			T1	26		T5	694		T8	17
valid_sources[0x08]	49528	1			T1	34		T3	43		T5	724
valid_sources[0x09]	58744	1			T1	39		T5	799		T8	24
valid_sources[0x0a]	66790	1			T1	29		T5	758		T8	27
valid_sources[0x0b]	61999	1			T1	52		T5	781		T8	20
valid_sources[0x0c]	54787	1			T1	42		T3	254		T5	759
valid_sources[0x0d]	49992	1			T1	37		T5	827		T8	14
valid_sources[0x0e]	50591	1			T1	40		T5	707		T8	17
valid_sources[0x0f]	67736	1			T1	30		T3	18		T5	821
valid_sources[0x10]	55944	1			T1	51		T3	86		T5	730
valid_sources[0x11]	49920	1			T1	46		T5	780		T8	12
valid_sources[0x12]	46907	1			T1	41		T4	10		T5	726
valid_sources[0x13]	51894	1			T1	50		T5	796		T8	15
valid_sources[0x14]	48688	1			T1	40		T5	742		T8	17
valid_sources[0x15]	57347	1			T1	19		T4	9		T5	810
valid_sources[0x16]	54973	1			T1	27		T5	741		T8	19
valid_sources[0x17]	60480	1			T1	36		T3	34		T5	791
valid_sources[0x18]	54754	1			T1	37		T5	787		T8	16
valid_sources[0x19]	51252	1			T1	38		T5	717		T8	16
valid_sources[0x1a]	61022	1			T1	35		T4	87		T5	711
valid_sources[0x1b]	49846	1			T1	42		T5	766		T8	21
valid_sources[0x1c]	50961	1			T1	40		T3	71		T5	714
valid_sources[0x1d]	56212	1			T1	34		T5	794		T8	17
valid_sources[0x1e]	51695	1			T1	36		T5	762		T8	17
valid_sources[0x1f]	49708	1			T1	43		T3	12		T5	777
valid_sources[0x20]	55462	1			T1	41		T3	319		T5	757
valid_sources[0x21]	51152	1			T1	49		T4	51		T5	761
valid_sources[0x22]	48094	1			T1	40		T3	147		T5	786
valid_sources[0x23]	49277	1			T1	47		T5	744		T8	24
valid_sources[0x24]	49723	1			T1	45		T5	712		T8	16
valid_sources[0x25]	52562	1			T1	24		T4	301		T5	790
valid_sources[0x26]	48104	1			T1	27		T3	27		T5	804
valid_sources[0x27]	58845	1			T1	32		T3	32		T5	798
valid_sources[0x28]	52124	1			T1	21		T5	714		T8	19
valid_sources[0x29]	52047	1			T1	37		T5	742		T8	15
valid_sources[0x2a]	63980	1			T1	27		T5	784		T8	13
valid_sources[0x2b]	50308	1			T1	36		T4	570		T5	717
valid_sources[0x2c]	77275	1			T1	40		T5	637		T8	18
valid_sources[0x2d]	53276	1			T1	45		T5	747		T8	17
valid_sources[0x2e]	56975	1			T1	26		T5	804		T8	21
valid_sources[0x2f]	125973	1			T1	13		T3	11		T5	742
valid_sources[0x30]	48210	1			T1	52		T4	35		T5	740
valid_sources[0x31]	52500	1			T1	20		T4	88		T5	769
valid_sources[0x32]	50882	1			T1	41		T5	741		T8	21
valid_sources[0x33]	49720	1			T1	32		T3	25		T5	715
valid_sources[0x34]	50577	1			T1	34		T3	18		T4	174
valid_sources[0x35]	53986	1			T1	31		T5	723		T8	20
valid_sources[0x36]	56936	1			T1	53		T3	146		T4	45
valid_sources[0x37]	49223	1			T1	49		T5	722		T8	19
valid_sources[0x38]	67415	1			T1	25		T5	771		T8	22
valid_sources[0x39]	58594	1			T1	35		T5	775		T8	7
valid_sources[0x3a]	52823	1			T1	46		T5	746		T8	16
valid_sources[0x3b]	52095	1			T1	50		T3	51		T5	732
valid_sources[0x3c]	48380	1			T1	42		T5	817		T8	22
valid_sources[0x3d]	55530	1			T1	35		T5	778		T8	11
valid_sources[0x3e]	63048	1			T1	32		T3	63		T5	718
valid_sources[0x3f]	57958	1			T1	24		T3	233		T5	775
valid_sources[0x40]	49502	1			T1	37		T5	779		T8	26
valid_sources[0x41]	49423	1			T1	34		T5	815		T8	22
valid_sources[0x42]	50667	1			T1	34		T3	230		T5	754
valid_sources[0x43]	53290	1			T1	42		T5	702		T8	14
valid_sources[0x44]	49512	1			T1	29		T5	803		T8	24
valid_sources[0x45]	57988	1			T1	44		T5	759		T8	19
valid_sources[0x46]	57459	1			T1	55		T3	8		T5	766
valid_sources[0x47]	58175	1			T1	32		T5	690		T8	24
valid_sources[0x48]	57340	1			T1	34		T5	779		T8	26
valid_sources[0x49]	52570	1			T1	36		T3	96		T5	717
valid_sources[0x4a]	51044	1			T1	39		T5	764		T8	28
valid_sources[0x4b]	50643	1			T1	47		T3	109		T5	709
valid_sources[0x4c]	49173	1			T1	42		T3	31		T5	725
valid_sources[0x4d]	53689	1			T1	35		T5	796		T8	15
valid_sources[0x4e]	61658	1			T1	21		T3	20		T5	821
valid_sources[0x4f]	53550	1			T1	42		T3	14		T5	772
valid_sources[0x50]	50488	1			T1	26		T4	27		T5	754
valid_sources[0x51]	50218	1			T1	31		T3	16		T5	680
valid_sources[0x52]	50258	1			T1	53		T5	765		T8	24
valid_sources[0x53]	60751	1			T1	47		T5	734		T8	19
valid_sources[0x54]	49590	1			T1	37		T5	730		T8	28
valid_sources[0x55]	56163	1			T1	39		T5	776		T8	15
valid_sources[0x56]	60670	1			T1	33		T5	831		T8	13
valid_sources[0x57]	49572	1			T1	34		T5	737		T8	19
valid_sources[0x58]	52870	1			T1	33		T5	782		T8	20
valid_sources[0x59]	60695	1			T1	20		T3	145		T5	722
valid_sources[0x5a]	49933	1			T1	38		T3	11		T4	9
valid_sources[0x5b]	54245	1			T1	42		T5	804		T8	28
valid_sources[0x5c]	53329	1			T1	33		T5	743		T8	23
valid_sources[0x5d]	54734	1			T1	36		T3	43		T5	802
valid_sources[0x5e]	48288	1			T1	43		T3	37		T5	750
valid_sources[0x5f]	48711	1			T1	31		T5	761		T8	14
valid_sources[0x60]	51556	1			T1	28		T3	149		T5	775
valid_sources[0x61]	49883	1			T1	31		T5	746		T8	23
valid_sources[0x62]	57473	1			T1	46		T5	728		T8	11
valid_sources[0x63]	58045	1			T1	25		T5	787		T8	19
valid_sources[0x64]	48932	1			T1	35		T5	739		T8	22
valid_sources[0x65]	51209	1			T1	27		T3	188		T4	184
valid_sources[0x66]	54565	1			T1	40		T5	816		T8	23
valid_sources[0x67]	50911	1			T1	45		T4	17		T5	734
valid_sources[0x68]	60220	1			T1	47		T5	731		T8	18
valid_sources[0x69]	108957	1			T1	34		T3	223		T5	736
valid_sources[0x6a]	49829	1			T1	31		T3	86		T5	762
valid_sources[0x6b]	52402	1			T1	34		T5	772		T8	12
valid_sources[0x6c]	49817	1			T1	32		T5	698		T8	16
valid_sources[0x6d]	48471	1			T1	64		T4	142		T5	811
valid_sources[0x6e]	60057	1			T1	29		T5	796		T8	23
valid_sources[0x6f]	48999	1			T1	48		T3	74		T5	744
valid_sources[0x70]	49253	1			T1	30		T5	793		T8	27
valid_sources[0x71]	49434	1			T1	35		T5	735		T8	18
valid_sources[0x72]	46641	1			T1	37		T5	763		T8	15
valid_sources[0x73]	67228	1			T1	60		T5	831		T8	19
valid_sources[0x74]	53055	1			T1	40		T5	810		T8	17
valid_sources[0x75]	48902	1			T1	36		T5	785		T8	18
valid_sources[0x76]	50407	1			T1	44		T3	18		T4	233
valid_sources[0x77]	47443	1			T1	28		T3	109		T5	733
valid_sources[0x78]	63228	1			T1	36		T5	698		T8	19
valid_sources[0x79]	56578	1			T1	28		T3	9		T5	713
valid_sources[0x7a]	84622	1			T1	34		T3	163		T5	718
valid_sources[0x7b]	51881	1			T1	36		T5	805		T8	19
valid_sources[0x7c]	46275	1			T1	32		T3	42		T5	797
valid_sources[0x7d]	59549	1			T1	46		T5	774		T8	19
valid_sources[0x7e]	50046	1			T1	48		T5	825		T8	12
valid_sources[0x7f]	53956	1			T1	23		T5	855		T8	17
valid_sources[0x80]	50101	1			T1	54		T5	782		T8	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3386260

1

T1

1880

T2

1178

T3

514

values[0x0]

all_enables

biggest_size

1817360

1

T1

133

T2

84

T3

88

values[0x1]

all_enables

biggest_size

1738922

1

T1

85

T2

50

T3

63

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	233701	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

8475258

1

T1

160

T2

140

T3

180

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2169106	1			T1	80		T2	70		T3	90
values[0x0]	3177759	1			T1	35		T2	36		T3	43
values[0x1]	3362094	1			T1	45		T2	34		T3	47

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	84578	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8624381

1

T1

160

T2

140

T3

180

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	33982	1			T1	1		T2	2		T3	5
valid_sources[0x01]	32626	1			T1	2		T2	1		T5	929
valid_sources[0x02]	33099	1			T1	1		T2	1		T5	843
valid_sources[0x03]	34531	1			T5	946		T9	5		T12	1
valid_sources[0x04]	35996	1			T1	1		T2	2		T5	872
valid_sources[0x05]	32853	1			T5	931		T9	16		T12	1
valid_sources[0x06]	35514	1			T1	1		T2	1		T5	981
valid_sources[0x07]	34363	1			T1	1		T2	1		T5	968
valid_sources[0x08]	34855	1			T3	2		T5	950		T12	1
valid_sources[0x09]	32510	1			T1	1		T4	4		T5	961
valid_sources[0x0a]	33459	1			T1	2		T5	868		T90	1
valid_sources[0x0b]	34577	1			T1	3		T5	935		T102	1
valid_sources[0x0c]	32725	1			T3	7		T5	964		T9	12
valid_sources[0x0d]	34188	1			T2	1		T5	844		T12	1
valid_sources[0x0e]	33328	1			T1	1		T5	954		T12	2
valid_sources[0x0f]	33723	1			T1	2		T2	1		T5	991
valid_sources[0x10]	33776	1			T1	1		T2	2		T5	968
valid_sources[0x11]	33016	1			T2	1		T5	934		T12	2
valid_sources[0x12]	33127	1			T1	1		T3	1		T5	915
valid_sources[0x13]	34142	1			T5	908		T12	1		T90	3
valid_sources[0x14]	32776	1			T1	2		T5	914		T9	10
valid_sources[0x15]	33274	1			T1	1		T2	2		T5	904
valid_sources[0x16]	33746	1			T2	1		T5	992		T100	4
valid_sources[0x17]	35483	1			T1	2		T5	940		T12	2
valid_sources[0x18]	34729	1			T1	1		T2	1		T5	906
valid_sources[0x19]	32076	1			T1	1		T2	1		T5	904
valid_sources[0x1a]	35170	1			T1	2		T5	937		T12	2
valid_sources[0x1b]	34755	1			T1	1		T2	1		T5	963
valid_sources[0x1c]	34986	1			T5	954		T100	1		T90	1
valid_sources[0x1d]	32555	1			T1	1		T5	969		T9	6
valid_sources[0x1e]	33620	1			T2	1		T5	906		T9	10
valid_sources[0x1f]	32550	1			T3	2		T5	925		T9	6
valid_sources[0x20]	33681	1			T2	2		T5	974		T12	1
valid_sources[0x21]	35989	1			T5	957		T12	1		T90	1
valid_sources[0x22]	33687	1			T1	1		T5	978		T8	6
valid_sources[0x23]	33706	1			T2	2		T5	885		T90	2
valid_sources[0x24]	32743	1			T5	924		T90	1		T102	2
valid_sources[0x25]	33822	1			T1	1		T2	2		T3	9
valid_sources[0x26]	33095	1			T1	1		T5	904		T9	1
valid_sources[0x27]	36487	1			T1	1		T5	891		T8	6
valid_sources[0x28]	34979	1			T5	980		T9	3		T12	3
valid_sources[0x29]	34497	1			T1	4		T2	1		T5	899
valid_sources[0x2a]	33835	1			T1	4		T2	2		T5	901
valid_sources[0x2b]	33049	1			T1	3		T5	937		T90	4
valid_sources[0x2c]	33380	1			T1	1		T5	915		T102	2
valid_sources[0x2d]	33054	1			T1	1		T5	916		T9	2
valid_sources[0x2e]	33816	1			T5	974		T157	1		T102	1
valid_sources[0x2f]	34186	1			T2	1		T5	980		T7	569
valid_sources[0x30]	35089	1			T2	1		T5	976		T9	12
valid_sources[0x31]	34107	1			T5	935		T102	2		T103	3
valid_sources[0x32]	34574	1			T5	915		T9	2		T12	1
valid_sources[0x33]	35031	1			T2	3		T5	961		T9	7
valid_sources[0x34]	33578	1			T1	1		T2	1		T5	890
valid_sources[0x35]	35754	1			T2	2		T5	919		T8	2
valid_sources[0x36]	34819	1			T1	1		T5	961		T9	4
valid_sources[0x37]	34182	1			T1	2		T2	2		T5	928
valid_sources[0x38]	34603	1			T5	906		T8	6		T9	2
valid_sources[0x39]	35193	1			T1	2		T3	3		T5	964
valid_sources[0x3a]	33812	1			T2	1		T3	5		T5	978
valid_sources[0x3b]	31912	1			T1	3		T2	1		T5	964
valid_sources[0x3c]	32576	1			T1	1		T5	944		T12	1
valid_sources[0x3d]	33567	1			T5	958		T9	31		T90	1
valid_sources[0x3e]	35918	1			T1	1		T5	971		T9	25
valid_sources[0x3f]	33136	1			T1	1		T2	1		T5	941
valid_sources[0x40]	34597	1			T3	2		T5	916		T9	5
valid_sources[0x41]	35365	1			T1	1		T5	971		T102	1
valid_sources[0x42]	34807	1			T1	1		T2	1		T3	1
valid_sources[0x43]	33492	1			T1	1		T2	1		T3	4
valid_sources[0x44]	34429	1			T3	6		T5	977		T12	1
valid_sources[0x45]	36541	1			T5	894		T12	2		T100	1
valid_sources[0x46]	33129	1			T5	902		T9	23		T90	2
valid_sources[0x47]	34308	1			T5	968		T12	1		T97	4
valid_sources[0x48]	36260	1			T2	1		T5	955		T12	4
valid_sources[0x49]	36916	1			T3	2		T5	960		T9	6
valid_sources[0x4a]	32469	1			T2	1		T3	1		T5	948
valid_sources[0x4b]	35413	1			T5	923		T102	2		T158	1
valid_sources[0x4c]	34849	1			T2	1		T5	931		T12	1
valid_sources[0x4d]	34678	1			T4	27		T5	930		T84	1
valid_sources[0x4e]	35260	1			T1	2		T5	984		T12	1
valid_sources[0x4f]	33903	1			T2	1		T5	911		T12	2
valid_sources[0x50]	34064	1			T1	3		T2	1		T5	882
valid_sources[0x51]	33090	1			T2	1		T5	902		T12	1
valid_sources[0x52]	33599	1			T1	1		T3	2		T5	978
valid_sources[0x53]	34858	1			T5	914		T9	1		T90	1
valid_sources[0x54]	33840	1			T3	1		T5	949		T9	1
valid_sources[0x55]	34305	1			T1	1		T3	1		T5	930
valid_sources[0x56]	33420	1			T1	1		T5	899		T12	2
valid_sources[0x57]	33376	1			T1	1		T5	1004		T12	1
valid_sources[0x58]	34760	1			T2	2		T5	923		T9	4
valid_sources[0x59]	33014	1			T1	1		T3	2		T5	940
valid_sources[0x5a]	33982	1			T2	1		T5	1001		T9	11
valid_sources[0x5b]	33831	1			T1	1		T2	1		T5	958
valid_sources[0x5c]	36026	1			T2	1		T3	1		T5	952
valid_sources[0x5d]	33452	1			T1	3		T5	919		T12	1
valid_sources[0x5e]	33305	1			T1	1		T5	948		T9	5
valid_sources[0x5f]	33648	1			T1	1		T2	1		T5	934
valid_sources[0x60]	32561	1			T5	915		T9	1		T102	3
valid_sources[0x61]	33664	1			T1	1		T5	936		T9	1
valid_sources[0x62]	32965	1			T1	2		T2	1		T5	888
valid_sources[0x63]	33359	1			T1	2		T2	2		T5	975
valid_sources[0x64]	33985	1			T1	2		T2	1		T5	941
valid_sources[0x65]	33951	1			T1	1		T5	932		T8	1
valid_sources[0x66]	35199	1			T2	1		T3	1		T5	876
valid_sources[0x67]	33828	1			T2	1		T3	1		T5	956
valid_sources[0x68]	33398	1			T1	1		T5	888		T9	3
valid_sources[0x69]	34228	1			T1	1		T5	924		T12	1
valid_sources[0x6a]	33761	1			T5	945		T9	7		T100	1
valid_sources[0x6b]	34203	1			T1	1		T5	925		T15	20
valid_sources[0x6c]	34719	1			T2	1		T5	959		T12	2
valid_sources[0x6d]	33392	1			T1	1		T2	1		T3	1
valid_sources[0x6e]	34166	1			T1	1		T5	1031		T90	2
valid_sources[0x6f]	33321	1			T1	1		T2	1		T5	950
valid_sources[0x70]	34734	1			T1	1		T5	905		T9	3
valid_sources[0x71]	32336	1			T2	1		T3	4		T5	940
valid_sources[0x72]	35315	1			T2	1		T5	928		T9	12
valid_sources[0x73]	33478	1			T1	1		T2	1		T5	954
valid_sources[0x74]	33536	1			T1	1		T2	1		T5	938
valid_sources[0x75]	33356	1			T2	1		T5	943		T12	2
valid_sources[0x76]	33743	1			T5	930		T9	7		T12	6
valid_sources[0x77]	34611	1			T1	1		T5	943		T12	1
valid_sources[0x78]	33752	1			T1	1		T2	2		T5	960
valid_sources[0x79]	34460	1			T5	933		T90	3		T102	2
valid_sources[0x7a]	32481	1			T1	1		T2	1		T5	939
valid_sources[0x7b]	33102	1			T5	944		T90	3		T6	2
valid_sources[0x7c]	33948	1			T1	1		T5	935		T9	6
valid_sources[0x7d]	34825	1			T1	1		T3	11		T5	932
valid_sources[0x7e]	34785	1			T2	1		T5	926		T7	516
valid_sources[0x7f]	33975	1			T3	5		T5	886		T12	1
valid_sources[0x80]	33042	1			T2	1		T5	934		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2155369

1

T1

80

T2

70

T3

90

values[0x0]

all_enables

biggest_size

3161855

1

T1

35

T2

36

T3

43

values[0x1]

all_enables

biggest_size

3158034

1

T1

45

T2

34

T3

47