Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

24066069

1

T1

7505

T2

1639

T3

5247

full_word

7963334

1

T1

2098

T2

1312

T3

665

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32029093	1			T1	9603		T2	2951		T3	5912
auto[TlIntgErrCmd]	89	1			T260	2		T261	7		T262	6
auto[TlIntgErrData]	124	1			T260	5		T261	3		T262	8
auto[TlIntgErrBoth]	97	1			T260	3		T261	10		T262	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9594874

1

T1

9025

T2

2619

T3

5551

auto[1]

22434529

1

T1

578

T2

332

T3

361

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6083636	1			T1	7145		T2	1441		T3	5037
auto[TlIntgErrNone]	partial	auto[1]	17982144	1			T1	360		T2	198		T3	210
auto[TlIntgErrNone]	full_word	auto[0]	3511102	1			T1	1880		T2	1178		T3	514
auto[TlIntgErrNone]	full_word	auto[1]	4452211	1			T1	218		T2	134		T3	151
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T260	1		T261	3		T262	2
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T260	1		T261	4		T262	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T262	1		T336	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T262	1		T266	1		T337	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T260	1		T261	3		T262	2
auto[TlIntgErrData]	partial	auto[1]	62	1			T260	4		T262	5		T267	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T262	1		T266	1		T338	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T267	1		T337	1		T339	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T260	3		T261	6		T262	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T261	3		T262	4		T267	2
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T261	1		T267	1		T340	1