Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	96.96		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	464955638	7602434	0	0
check_regwen_rd_A	464955638	3459	0	0
check_timeout_rd_A	464955638	2710	0	0
check_trigger_regwen_rd_A	464955638	3345	0	0
consistency_check_period_rd_A	464955638	3310	0	0
creator_sw_cfg_read_lock_rd_A	464955638	2663	0	0
direct_access_address_rd_A	464955638	2500	0	0
direct_access_wdata_0_rd_A	464955638	1736	0	0
direct_access_wdata_1_rd_A	464955638	1801	0	0
integrity_check_period_rd_A	464955638	3290	0	0
intr_enable_rd_A	464955638	4335	0	0
owner_sw_cfg_read_lock_rd_A	464955638	2456	0	0
rot_creator_auth_codesign_read_lock_rd_A	464955638	2983	0	0
rot_creator_auth_state_read_lock_rd_A	464955638	2521	0	0
vendor_test_read_lock_rd_A	464955638	2560	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464955638	7602434	0	0
T5	716561	215488	0	0
T7	0	113150	0	0
T8	18163	0	0	0
T9	787573	0	0	0
T10	10137	0	0	0
T11	14486	0	0	0
T12	120210	0	0	0
T13	0	44775	0	0
T15	13749	0	0	0
T16	0	81231	0	0
T17	0	86753	0	0
T18	0	72943	0	0
T19	0	24662	0	0
T90	74059	0	0	0
T100	47176	0	0	0
T101	71021	0	0	0
T191	0	39973	0	0
T205	0	35764	0	0
T223	0	25199	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464955638	3459	0	0
T17	309080	0	0	0
T18	0	51	0	0
T20	0	73	0	0
T54	15281	0	0	0
T93	56995	0	0	0
T94	64005	0	0	0
T95	197963	0	0	0
T96	225269	0	0	0
T122	0	54	0	0
T144	16848	0	0	0
T166	22834	0	0	0
T191	279394	71	0	0
T217	12330	0	0	0
T223	0	51	0	0
T224	0	23	0	0
T242	0	159	0	0
T312	0	330	0	0
T321	0	162	0	0
T322	0	21	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464955638	2710	0	0
T17	309080	0	0	0
T18	0	53	0	0
T20	0	109	0	0
T54	15281	0	0	0
T93	56995	0	0	0
T94	64005	0	0	0
T95	197963	0	0	0
T96	225269	0	0	0
T122	0	39	0	0
T144	16848	0	0	0
T166	22834	0	0	0
T191	279394	94	0	0
T217	12330	0	0	0
T223	0	68	0	0
T224	0	21	0	0
T242	0	214	0	0
T312	0	239	0	0
T321	0	92	0	0
T322	0	34	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464955638	3345	0	0
T17	309080	0	0	0
T18	0	64	0	0
T20	0	83	0	0
T54	15281	0	0	0
T93	56995	0	0	0
T94	64005	0	0	0
T95	197963	0	0	0
T96	225269	0	0	0
T122	0	54	0	0
T144	16848	0	0	0
T166	22834	0	0	0
T191	279394	70	0	0
T217	12330	0	0	0
T223	0	44	0	0
T224	0	35	0	0
T242	0	164	0	0
T312	0	252	0	0
T321	0	121	0	0
T322	0	38	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464955638	3310	0	0
T17	309080	0	0	0
T18	0	59	0	0
T20	0	91	0	0
T54	15281	0	0	0
T93	56995	0	0	0
T94	64005	0	0	0
T95	197963	0	0	0
T96	225269	0	0	0
T122	0	39	0	0
T144	16848	0	0	0
T166	22834	0	0	0
T191	279394	95	0	0
T217	12330	0	0	0
T223	0	35	0	0
T224	0	19	0	0
T242	0	137	0	0
T312	0	281	0	0
T321	0	102	0	0
T322	0	8	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464955638	2663	0	0
T17	309080	0	0	0
T18	0	43	0	0
T20	0	73	0	0
T54	15281	0	0	0
T93	56995	0	0	0
T94	64005	0	0	0
T95	197963	0	0	0
T96	225269	0	0	0
T122	0	69	0	0
T144	16848	0	0	0
T166	22834	0	0	0
T191	279394	98	0	0
T217	12330	0	0	0
T223	0	80	0	0
T224	0	26	0	0
T242	0	176	0	0
T312	0	248	0	0
T321	0	173	0	0
T322	0	15	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464955638	2500	0	0
T17	309080	0	0	0
T18	0	58	0	0
T20	0	119	0	0
T54	15281	0	0	0
T93	56995	0	0	0
T94	64005	0	0	0
T95	197963	0	0	0
T96	225269	0	0	0
T122	0	73	0	0
T144	16848	0	0	0
T166	22834	0	0	0
T191	279394	90	0	0
T217	12330	0	0	0
T223	0	58	0	0
T224	0	34	0	0
T242	0	208	0	0
T312	0	292	0	0
T321	0	165	0	0
T322	0	9	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464955638	1736	0	0
T17	309080	0	0	0
T18	0	32	0	0
T20	0	67	0	0
T54	15281	0	0	0
T93	56995	0	0	0
T94	64005	0	0	0
T95	197963	0	0	0
T96	225269	0	0	0
T122	0	26	0	0
T144	16848	0	0	0
T166	22834	0	0	0
T191	279394	30	0	0
T217	12330	0	0	0
T223	0	27	0	0
T224	0	31	0	0
T242	0	126	0	0
T312	0	217	0	0
T321	0	114	0	0
T322	0	19	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464955638	1801	0	0
T17	309080	0	0	0
T18	0	29	0	0
T20	0	63	0	0
T54	15281	0	0	0
T93	56995	0	0	0
T94	64005	0	0	0
T95	197963	0	0	0
T96	225269	0	0	0
T122	0	18	0	0
T144	16848	0	0	0
T166	22834	0	0	0
T191	279394	40	0	0
T217	12330	0	0	0
T223	0	17	0	0
T224	0	42	0	0
T242	0	196	0	0
T312	0	278	0	0
T321	0	119	0	0
T322	0	5	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464955638	3290	0	0
T17	309080	0	0	0
T18	0	50	0	0
T20	0	78	0	0
T54	15281	0	0	0
T93	56995	0	0	0
T94	64005	0	0	0
T95	197963	0	0	0
T96	225269	0	0	0
T122	0	70	0	0
T144	16848	0	0	0
T166	22834	0	0	0
T191	279394	79	0	0
T217	12330	0	0	0
T223	0	52	0	0
T224	0	29	0	0
T242	0	165	0	0
T312	0	260	0	0
T321	0	147	0	0
T322	0	33	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464955638	4335	0	0
T17	309080	0	0	0
T18	0	55	0	0
T20	0	114	0	0
T54	15281	0	0	0
T93	56995	0	0	0
T94	64005	0	0	0
T95	197963	0	0	0
T96	225269	0	0	0
T122	0	59	0	0
T144	16848	0	0	0
T166	22834	0	0	0
T191	279394	86	0	0
T217	12330	0	0	0
T223	0	23	0	0
T224	0	45	0	0
T242	0	147	0	0
T312	0	256	0	0
T321	0	112	0	0
T322	0	63	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464955638	2456	0	0
T17	309080	0	0	0
T18	0	55	0	0
T20	0	86	0	0
T54	15281	0	0	0
T93	56995	0	0	0
T94	64005	0	0	0
T95	197963	0	0	0
T96	225269	0	0	0
T122	0	54	0	0
T144	16848	0	0	0
T166	22834	0	0	0
T191	279394	84	0	0
T217	12330	0	0	0
T223	0	66	0	0
T224	0	17	0	0
T242	0	132	0	0
T312	0	276	0	0
T321	0	127	0	0
T322	0	36	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464955638	2983	0	0
T17	309080	0	0	0
T18	0	134	0	0
T20	0	103	0	0
T54	15281	0	0	0
T93	56995	0	0	0
T94	64005	0	0	0
T95	197963	0	0	0
T96	225269	0	0	0
T122	0	59	0	0
T144	16848	0	0	0
T166	22834	0	0	0
T191	279394	81	0	0
T217	12330	0	0	0
T223	0	47	0	0
T224	0	9	0	0
T242	0	228	0	0
T312	0	390	0	0
T321	0	123	0	0
T322	0	51	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464955638	2521	0	0
T17	309080	0	0	0
T18	0	48	0	0
T20	0	103	0	0
T54	15281	0	0	0
T93	56995	0	0	0
T94	64005	0	0	0
T95	197963	0	0	0
T96	225269	0	0	0
T122	0	50	0	0
T144	16848	0	0	0
T166	22834	0	0	0
T191	279394	84	0	0
T217	12330	0	0	0
T223	0	25	0	0
T224	0	31	0	0
T242	0	109	0	0
T312	0	316	0	0
T321	0	120	0	0
T322	0	36	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464955638	2560	0	0
T17	309080	0	0	0
T18	0	40	0	0
T20	0	54	0	0
T54	15281	0	0	0
T93	56995	0	0	0
T94	64005	0	0	0
T95	197963	0	0	0
T96	225269	0	0	0
T122	0	51	0	0
T144	16848	0	0	0
T166	22834	0	0	0
T191	279394	51	0	0
T217	12330	0	0	0
T223	0	32	0	0
T224	0	29	0	0
T242	0	195	0	0
T312	0	355	0	0
T321	0	111	0	0
T322	0	52	0	0