Unified Coverage Report :: Module :: otp_ctrl_scrmbl

Module : otp_ctrl_scrmbl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.95	91.67	100.00		100.00	98.08	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_scrmbl	98.33	91.67	100.00		100.00	100.00	100.00

---

Module Instance : tb.dut.u_otp_ctrl_scrmbl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	91.67	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.92	81.50	100.00	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	96.96		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_anchor_digests[0].u_const_anchor_buf	0.00	0.00
gen_anchor_digests[0].u_iv_anchor_buf	0.00	0.00
gen_anchor_digests[1].u_const_anchor_buf	0.00	0.00
gen_anchor_digests[1].u_iv_anchor_buf	0.00	0.00
gen_anchor_digests[2].u_const_anchor_buf	0.00	0.00
gen_anchor_digests[2].u_iv_anchor_buf	0.00	0.00
gen_anchor_digests[3].u_const_anchor_buf	0.00	0.00
gen_anchor_digests[3].u_iv_anchor_buf	0.00	0.00
gen_anchor_keys[0].u_key_anchor_buf	0.00	0.00
gen_anchor_keys[1].u_key_anchor_buf	0.00	0.00
gen_anchor_keys[2].u_key_anchor_buf	0.00	0.00
u_prim_count	100.00			100.00
u_prim_present_dec	100.00	100.00	100.00			100.00	100.00
u_prim_present_enc	100.00	100.00	100.00			100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : otp_ctrl_scrmbl

	Line No.	Total	Covered	Percent
TOTAL		120	110	91.67
ALWAYS	141	10	0	0.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
ALWAYS	302	75	75	100.00
ALWAYS	476	3	3	100.00
ALWAYS	479	21	21	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
141	0	1
142	0	1
143	0	1
144	0	1
146	0	1
148	0	1
151	0	1
155	0	1
156	0	1
157	0	1
199	1	1
200	1	1
201	1	1
202	1	1
209	1	1
215	1	1
224	1	1
230	1	1
231	1	1
234	1	1
281	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
311	1	1
312	1	1
313	1	1
314	1	1
315	1	1
316	1	1
318	1	1
323	1	1
324	1	1
326	1	1
327	1	1
329	1	1
330	1	1
331	1	1
332	1	1
335	1	1
336	1	1
337	1	1
338	1	1
341	1	1
342	1	1
344	1	1
348	1	1
349	1	1
350	1	1
351	1	1
352	1	1
355	1	1
356	1	1
357	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
			MISSING_ELSE
374	1	1
375	1	1
376	1	1
377	1	1
378	1	1
379	1	1
380	1	1
381	1	1
			MISSING_ELSE
387	1	1
388	1	1
389	1	1
390	1	1
391	1	1
392	1	1
393	1	1
394	1	1
			MISSING_ELSE
401	1	1
402	1	1
403	1	1
404	1	1
405	1	1
406	1	1
407	1	1
408	1	1
410	1	1
414	1	1
			MISSING_ELSE
420	1	1
434	1	1
435	1	1
436	1	1
			MISSING_ELSE
476	3	3
479	1	1
480	1	1
481	1	1
482	1	1
483	1	1
484	1	1
485	1	1
486	1	1
488	1	1
489	1	1
492	1	1
493	1	1
494	1	1
			MISSING_ELSE
496	1	1
497	1	1
			MISSING_ELSE
499	1	1
500	1	1
501	1	1
502	1	1
			MISSING_ELSE
504	1	1
505	1	1
			MISSING_ELSE

---

Cond Coverage for Module : otp_ctrl_scrmbl

	Total	Covered	Percent
Conditions	68	68	100.00
Logical	68	68	100.00
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION 
 Number  Term
      1  (data_state_sel == SelEncDataOut) ? enc_data_out : ((data_state_sel == SelDecDataOut) ? dec_data_out : ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       209
 SUB-EXPRESSION (data_state_sel == SelEncDataOut)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       209
 SUB-EXPRESSION 
 Number  Term
      1  (data_state_sel == SelDecDataOut) ? dec_data_out : ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       209
 SUB-EXPRESSION (data_state_sel == SelDecDataOut)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       209
 SUB-EXPRESSION ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       209
 SUB-EXPRESSION (data_state_sel == SelDigestState)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       209
 SUB-EXPRESSION ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i)
                 ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       209
 SUB-EXPRESSION (data_state_sel == SelEncDataOutXor)
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDecKeyOut) ? dec_key_out : ((key_state_sel == SelEncKeyOut) ? enc_key_out : ((key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelDecKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelEncKeyOut) ? enc_key_out : ((key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelEncKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelDecKeyInit)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelEncKeyInit)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelDigestConst)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))
                 -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelDigestChained)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       224
 EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDecKeyOut) ? dec_idx_out : ((key_state_sel == SelEncKeyOut) ? enc_idx_out : ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       224
 SUB-EXPRESSION (key_state_sel == SelDecKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       224
 SUB-EXPRESSION ((key_state_sel == SelEncKeyOut) ? enc_idx_out : ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1))
                 ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       224
 SUB-EXPRESSION (key_state_sel == SelEncKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       224
 SUB-EXPRESSION ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       224
 SUB-EXPRESSION (key_state_sel == SelDecKeyInit)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION (digest_init ? otp_digest_iv_mux : enc_data_out_xor)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION (valid_q ? data_state_q : 0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       341
 EXPRESSION (digest_mode_q == ChainedMode)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       350
 EXPRESSION ((digest_mode_q == ChainedMode) ? SelDigestChained : SelDigestInput)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       350
 SUB-EXPRESSION (digest_mode_q == ChainedMode)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       379
 EXPRESSION (cnt == LastPresentRound)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (cnt == LastPresentRound)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       406
 EXPRESSION (cnt == LastPresentRound)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : otp_ctrl_scrmbl

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	10	10	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DecryptSt	329	Covered	T1,T2,T3
DigestSt	348	Covered	T1,T2,T3
EncryptSt	335	Covered	T1,T2,T3
ErrorSt	435	Covered	T2,T8,T9
IdleSt	380	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DecryptSt->ErrorSt	435	Covered	T120,T121,T258
DecryptSt->IdleSt	380	Covered	T1,T2,T3
DigestSt->ErrorSt	435	Covered	T9,T200,T205
DigestSt->IdleSt	407	Covered	T1,T2,T3
EncryptSt->ErrorSt	435	Covered	T8,T114,T259
EncryptSt->IdleSt	393	Covered	T1,T2,T3
IdleSt->DecryptSt	329	Covered	T1,T2,T3
IdleSt->DigestSt	348	Covered	T1,T2,T3
IdleSt->EncryptSt	335	Covered	T1,T2,T3
IdleSt->ErrorSt	435	Covered	T2,T9,T100

---

Branch Coverage for Module : otp_ctrl_scrmbl

	Line No.	Total	Covered	Percent
Branches		52	51	98.08
TERNARY	209	5	5	100.00
TERNARY	215	7	7	100.00
TERNARY	224	4	4	100.00
TERNARY	231	2	2	100.00
TERNARY	234	2	2	100.00
CASE	318	18	17	94.44
IF	434	2	2	100.00
IF	476	2	2	100.00
IF	479	10	10	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	209	((data_state_sel == SelEncDataOut)) ? 
-2-:	209	((data_state_sel == SelDecDataOut)) ? 
-3-:	209	((data_state_sel == SelDigestState)) ? 
-4-:	209	((data_state_sel == SelEncDataOutXor)) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	((key_state_sel == SelDecKeyOut)) ? 
-2-:	215	((key_state_sel == SelEncKeyOut)) ? 
-3-:	215	((key_state_sel == SelDecKeyInit)) ? 
-4-:	215	((key_state_sel == SelEncKeyInit)) ? 
-5-:	215	((key_state_sel == SelDigestConst)) ? 
-6-:	215	((key_state_sel == SelDigestChained)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	-	Covered	T1,T2,T3
0	0	0	1	-	-	Covered	T1,T2,T3
0	0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	((key_state_sel == SelDecKeyOut)) ? 
-2-:	224	((key_state_sel == SelEncKeyOut)) ? 
-3-:	224	((key_state_sel == SelDecKeyInit)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	(digest_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	234	(valid_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	318	case (state_q)
-2-:	326	if (valid_i)
-3-:	327	case (cmd_i)
-4-:	341	if ((digest_mode_q == ChainedMode))
-5-:	350	((digest_mode_q == ChainedMode)) ? 
-6-:	379	if ((cnt == LastPresentRound))
-7-:	392	if ((cnt == LastPresentRound))
-8-:	406	if ((cnt == LastPresentRound))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	Decrypt	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	1	Encrypt	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	1	LoadShadow	1	-	-	-	-	Covered	T1,T2,T3
IdleSt	1	LoadShadow	0	-	-	-	-	Covered	T1,T2,T3
IdleSt	1	Digest	-	1	-	-	-	Covered	T1,T2,T3
IdleSt	1	Digest	-	0	-	-	-	Covered	T1,T2,T3
IdleSt	1	DigestInit	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	1	DigestFinalize	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	1	default	-	-	-	-	-	Not Covered
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DecryptSt	-	-	-	-	1	-	-	Covered	T1,T2,T3
DecryptSt	-	-	-	-	0	-	-	Covered	T1,T2,T3
EncryptSt	-	-	-	-	-	1	-	Covered	T1,T2,T3
EncryptSt	-	-	-	-	-	0	-	Covered	T1,T2,T3
DigestSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
DigestSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	Covered	T2,T8,T9
default	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	434	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	476	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	479	if ((!rst_ni))
-2-:	492	if (key_state_en)
-3-:	496	if (data_state_en)
-4-:	499	if (data_shadow_copy)
-5-:	501	if (data_shadow_load)
-6-:	504	if (digest_state_en)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T2,T3
0	0	-	-	-	-	Covered	T1,T2,T3
0	-	1	-	-	-	Covered	T1,T2,T3
0	-	0	-	-	-	Covered	T1,T2,T3
0	-	-	1	-	-	Covered	T1,T2,T3
0	-	-	0	1	-	Covered	T1,T2,T3
0	-	-	0	0	-	Covered	T1,T2,T3
0	-	-	-	-	1	Covered	T1,T2,T3
0	-	-	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_scrmbl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	9	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	9	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckNumDecKeys_A	461803720	251310	0	0
CheckNumDigest1_A	461803720	147646	0	0
CheckNumEncKeys_A	461803720	269340	0	0
DecKeyLutKnown_A	461803720	460938686	0	0
DigestConstLutKnown_A	461803720	460938686	0	0
DigestIvLutKnown_A	461803720	460938686	0	0
EncKeyLutKnown_A	461803720	460938686	0	0
NumMaxPresentRounds_A	1148	1148	0	0
u_state_regs_A	461803720	460938686	0	0

CheckNumDecKeys_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	251310	0	0
T1	68010	335	0	0
T2	40272	53	0	0
T3	67749	282	0	0
T4	36237	168	0	0
T5	716561	227	0	0
T8	18163	72	0	0
T9	787573	2219	0	0
T10	10137	61	0	0
T11	14486	50	0	0
T12	120210	447	0	0

CheckNumDigest1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	147646	0	0
T1	68010	175	0	0
T2	40272	13	0	0
T3	67749	221	0	0
T4	36237	95	0	0
T5	716561	406	0	0
T8	18163	13	0	0
T9	787573	1878	0	0
T10	10137	26	0	0
T11	14486	6	0	0
T12	120210	268	0	0

CheckNumEncKeys_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	269340	0	0
T1	68010	411	0	0
T2	40272	50	0	0
T3	67749	364	0	0
T4	36237	146	0	0
T5	716561	418	0	0
T8	18163	58	0	0
T9	787573	2177	0	0
T10	10137	53	0	0
T11	14486	38	0	0
T12	120210	508	0	0

DecKeyLutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

DigestConstLutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

DigestIvLutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

EncKeyLutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

NumMaxPresentRounds_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

Line Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl

	Line No.	Total	Covered	Percent
TOTAL		120	110	91.67
ALWAYS	141	10	0	0.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	209	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	231	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
ALWAYS	302	75	75	100.00
ALWAYS	476	3	3	100.00
ALWAYS	479	21	21	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
141	0	1
142	0	1
143	0	1
144	0	1
146	0	1
148	0	1
151	0	1
155	0	1
156	0	1
157	0	1
199	1	1
200	1	1
201	1	1
202	1	1
209	1	1
215	1	1
224	1	1
230	1	1
231	1	1
234	1	1
281	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
311	1	1
312	1	1
313	1	1
314	1	1
315	1	1
316	1	1
318	1	1
323	1	1
324	1	1
326	1	1
327	1	1
329	1	1
330	1	1
331	1	1
332	1	1
335	1	1
336	1	1
337	1	1
338	1	1
341	1	1
342	1	1
344	1	1
348	1	1
349	1	1
350	1	1
351	1	1
352	1	1
355	1	1
356	1	1
357	1	1
360	1	1
361	1	1
362	1	1
363	1	1
364	1	1
365	1	1
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
374	1	1
375	1	1
376	1	1
377	1	1
378	1	1
379	1	1
380	1	1
381	1	1
			MISSING_ELSE
387	1	1
388	1	1
389	1	1
390	1	1
391	1	1
392	1	1
393	1	1
394	1	1
			MISSING_ELSE
401	1	1
402	1	1
403	1	1
404	1	1
405	1	1
406	1	1
407	1	1
408	1	1
410	1	1
414	1	1
			MISSING_ELSE
420	1	1
434	1	1
435	1	1
436	1	1
			MISSING_ELSE
476	3	3
479	1	1
480	1	1
481	1	1
482	1	1
483	1	1
484	1	1
485	1	1
486	1	1
488	1	1
489	1	1
492	1	1
493	1	1
494	1	1
			MISSING_ELSE
496	1	1
497	1	1
			MISSING_ELSE
499	1	1
500	1	1
501	1	1
502	1	1
			MISSING_ELSE
504	1	1
505	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl

	Total	Covered	Percent
Conditions	68	68	100.00
Logical	68	68	100.00
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION 
 Number  Term
      1  (data_state_sel == SelEncDataOut) ? enc_data_out : ((data_state_sel == SelDecDataOut) ? dec_data_out : ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       209
 SUB-EXPRESSION (data_state_sel == SelEncDataOut)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       209
 SUB-EXPRESSION 
 Number  Term
      1  (data_state_sel == SelDecDataOut) ? dec_data_out : ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       209
 SUB-EXPRESSION (data_state_sel == SelDecDataOut)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       209
 SUB-EXPRESSION ((data_state_sel == SelDigestState) ? digest_state_q : ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       209
 SUB-EXPRESSION (data_state_sel == SelDigestState)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       209
 SUB-EXPRESSION ((data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : data_i)
                 ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       209
 SUB-EXPRESSION (data_state_sel == SelEncDataOutXor)
                ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDecKeyOut) ? dec_key_out : ((key_state_sel == SelEncKeyOut) ? enc_key_out : ((key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelDecKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelEncKeyOut) ? enc_key_out : ((key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelEncKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : ((key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelDecKeyInit)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : ((key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelEncKeyInit)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDigestConst) ? otp_digest_const_mux : ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q})))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelDigestConst)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION ((key_state_sel == SelDigestChained) ? ({data_state_q, data_shadow_q}) : ({data_i, data_shadow_q}))
                 -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       215
 SUB-EXPRESSION (key_state_sel == SelDigestChained)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       224
 EXPRESSION 
 Number  Term
      1  (key_state_sel == SelDecKeyOut) ? dec_idx_out : ((key_state_sel == SelEncKeyOut) ? enc_idx_out : ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       224
 SUB-EXPRESSION (key_state_sel == SelDecKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       224
 SUB-EXPRESSION ((key_state_sel == SelEncKeyOut) ? enc_idx_out : ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1))
                 ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       224
 SUB-EXPRESSION (key_state_sel == SelEncKeyOut)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       224
 SUB-EXPRESSION ((key_state_sel == SelDecKeyInit) ? ((unsigned'(5'(otp_ctrl_pkg::NumPresentRounds)))) : 5'b1)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       224
 SUB-EXPRESSION (key_state_sel == SelDecKeyInit)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       231
 EXPRESSION (digest_init ? otp_digest_iv_mux : enc_data_out_xor)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION (valid_q ? data_state_q : 0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       341
 EXPRESSION (digest_mode_q == ChainedMode)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       350
 EXPRESSION ((digest_mode_q == ChainedMode) ? SelDigestChained : SelDigestInput)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       350
 SUB-EXPRESSION (digest_mode_q == ChainedMode)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       379
 EXPRESSION (cnt == LastPresentRound)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       392
 EXPRESSION (cnt == LastPresentRound)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       406
 EXPRESSION (cnt == LastPresentRound)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	10	10	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DecryptSt	329	Covered	T1,T2,T3
DigestSt	348	Covered	T1,T2,T3
EncryptSt	335	Covered	T1,T2,T3
ErrorSt	435	Covered	T2,T8,T9
IdleSt	380	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DecryptSt->ErrorSt	435	Covered	T120,T121,T258
DecryptSt->IdleSt	380	Covered	T1,T2,T3
DigestSt->ErrorSt	435	Covered	T9,T200,T205
DigestSt->IdleSt	407	Covered	T1,T2,T3
EncryptSt->ErrorSt	435	Covered	T8,T114,T259
EncryptSt->IdleSt	393	Covered	T1,T2,T3
IdleSt->DecryptSt	329	Covered	T1,T2,T3
IdleSt->DigestSt	348	Covered	T1,T2,T3
IdleSt->EncryptSt	335	Covered	T1,T2,T3
IdleSt->ErrorSt	435	Covered	T2,T9,T100

---

Branch Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl

	Line No.	Total	Covered	Percent
Branches		51	51	100.00
TERNARY	209	5	5	100.00
TERNARY	215	7	7	100.00
TERNARY	224	4	4	100.00
TERNARY	231	2	2	100.00
TERNARY	234	2	2	100.00
CASE	318	17	17	100.00
IF	434	2	2	100.00
IF	476	2	2	100.00
IF	479	10	10	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_scrmbl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	209	((data_state_sel == SelEncDataOut)) ? 
-2-:	209	((data_state_sel == SelDecDataOut)) ? 
-3-:	209	((data_state_sel == SelDigestState)) ? 
-4-:	209	((data_state_sel == SelEncDataOutXor)) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T1,T2,T3
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	((key_state_sel == SelDecKeyOut)) ? 
-2-:	215	((key_state_sel == SelEncKeyOut)) ? 
-3-:	215	((key_state_sel == SelDecKeyInit)) ? 
-4-:	215	((key_state_sel == SelEncKeyInit)) ? 
-5-:	215	((key_state_sel == SelDigestConst)) ? 
-6-:	215	((key_state_sel == SelDigestChained)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	-	Covered	T1,T2,T3
0	0	0	1	-	-	Covered	T1,T2,T3
0	0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	224	((key_state_sel == SelDecKeyOut)) ? 
-2-:	224	((key_state_sel == SelEncKeyOut)) ? 
-3-:	224	((key_state_sel == SelDecKeyInit)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	231	(digest_init) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	234	(valid_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	318	case (state_q)
-2-:	326	if (valid_i)
-3-:	327	case (cmd_i)
-4-:	341	if ((digest_mode_q == ChainedMode))
-5-:	350	((digest_mode_q == ChainedMode)) ? 
-6-:	379	if ((cnt == LastPresentRound))
-7-:	392	if ((cnt == LastPresentRound))
-8-:	406	if ((cnt == LastPresentRound))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	Decrypt	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	1	Encrypt	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	1	LoadShadow	1	-	-	-	-	Covered	T1,T2,T3
IdleSt	1	LoadShadow	0	-	-	-	-	Covered	T1,T2,T3
IdleSt	1	Digest	-	1	-	-	-	Covered	T1,T2,T3
IdleSt	1	Digest	-	0	-	-	-	Covered	T1,T2,T3
IdleSt	1	DigestInit	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	1	DigestFinalize	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	1	default	-	-	-	-	-	Excluded		VC_COV_UNR
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DecryptSt	-	-	-	-	1	-	-	Covered	T1,T2,T3
DecryptSt	-	-	-	-	0	-	-	Covered	T1,T2,T3
EncryptSt	-	-	-	-	-	1	-	Covered	T1,T2,T3
EncryptSt	-	-	-	-	-	0	-	Covered	T1,T2,T3
DigestSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
DigestSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	Covered	T2,T8,T9
default	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	434	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	476	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	479	if ((!rst_ni))
-2-:	492	if (key_state_en)
-3-:	496	if (data_state_en)
-4-:	499	if (data_shadow_copy)
-5-:	501	if (data_shadow_load)
-6-:	504	if (digest_state_en)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T2,T3
0	0	-	-	-	-	Covered	T1,T2,T3
0	-	1	-	-	-	Covered	T1,T2,T3
0	-	0	-	-	-	Covered	T1,T2,T3
0	-	-	1	-	-	Covered	T1,T2,T3
0	-	-	0	1	-	Covered	T1,T2,T3
0	-	-	0	0	-	Covered	T1,T2,T3
0	-	-	-	-	1	Covered	T1,T2,T3
0	-	-	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_otp_ctrl_scrmbl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	9	9	100.00	9	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	9	9	100.00	9	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckNumDecKeys_A	461803720	251310	0	0
CheckNumDigest1_A	461803720	147646	0	0
CheckNumEncKeys_A	461803720	269340	0	0
DecKeyLutKnown_A	461803720	460938686	0	0
DigestConstLutKnown_A	461803720	460938686	0	0
DigestIvLutKnown_A	461803720	460938686	0	0
EncKeyLutKnown_A	461803720	460938686	0	0
NumMaxPresentRounds_A	1148	1148	0	0
u_state_regs_A	461803720	460938686	0	0

CheckNumDecKeys_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	251310	0	0
T1	68010	335	0	0
T2	40272	53	0	0
T3	67749	282	0	0
T4	36237	168	0	0
T5	716561	227	0	0
T8	18163	72	0	0
T9	787573	2219	0	0
T10	10137	61	0	0
T11	14486	50	0	0
T12	120210	447	0	0

CheckNumDigest1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	147646	0	0
T1	68010	175	0	0
T2	40272	13	0	0
T3	67749	221	0	0
T4	36237	95	0	0
T5	716561	406	0	0
T8	18163	13	0	0
T9	787573	1878	0	0
T10	10137	26	0	0
T11	14486	6	0	0
T12	120210	268	0	0

CheckNumEncKeys_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	269340	0	0
T1	68010	411	0	0
T2	40272	50	0	0
T3	67749	364	0	0
T4	36237	146	0	0
T5	716561	418	0	0
T8	18163	58	0	0
T9	787573	2177	0	0
T10	10137	53	0	0
T11	14486	38	0	0
T12	120210	508	0	0

DecKeyLutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

DigestConstLutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

DigestIvLutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

EncKeyLutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

NumMaxPresentRounds_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0