Unified Coverage Report :: Module

Module : prim_double_lfsr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_double_lfsr_0/rtl/prim_double_lfsr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr	100.00	100.00	100.00				100.00

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.95	100.00	100.00	51.81			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.16	100.00	89.61		100.00	91.18	100.00	u_otp_ctrl_lfsr_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_double_lfsr[0].u_prim_buf_input	100.00	100.00
gen_double_lfsr[0].u_prim_buf_output	100.00	100.00
gen_double_lfsr[0].u_prim_lfsr	51.81			51.81
gen_double_lfsr[1].u_prim_buf_input	100.00	100.00
gen_double_lfsr[1].u_prim_buf_output	100.00	100.00
gen_double_lfsr[1].u_prim_lfsr	51.81			51.81

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_double_lfsr

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	103	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_double_lfsr_0/rtl/prim_double_lfsr.sv' or '../src/lowrisc_prim_double_lfsr_0/rtl/prim_double_lfsr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
102	1	1
103	1	1

Cond Coverage for Module : prim_double_lfsr

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (lfsr_state[0] != lfsr_state[1])
            ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

Assert Coverage for Module : prim_double_lfsr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AssertConnected_A	1148	1148	0	0

AssertConnected_A

Name	Attempts	Real Successes
Total	1148	1148
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T8	1	1
T9	1	1
T10	1	1
T11	1	1
T12	1	1