Module Definition
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Module : prim_double_lfsr
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_double_lfsr_0/rtl/prim_double_lfsr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_otp_ctrl_lfsr_timer.u_prim_double_lfsr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.95 100.00 100.00 51.81 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.16 100.00 89.61 100.00 91.18 100.00 u_otp_ctrl_lfsr_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_double_lfsr[0].u_prim_buf_input 100.00 100.00
gen_double_lfsr[0].u_prim_buf_output 100.00 100.00
gen_double_lfsr[0].u_prim_lfsr 51.81 51.81
gen_double_lfsr[1].u_prim_buf_input 100.00 100.00
gen_double_lfsr[1].u_prim_buf_output 100.00 100.00
gen_double_lfsr[1].u_prim_lfsr 51.81 51.81


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_double_lfsr
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_double_lfsr_0/rtl/prim_double_lfsr.sv' or '../src/lowrisc_prim_double_lfsr_0/rtl/prim_double_lfsr.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
102 1 1
103 1 1


Cond Coverage for Module : prim_double_lfsr
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       103
 EXPRESSION (lfsr_state[0] != lfsr_state[1])
            ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T22,T23

Assert Coverage for Module : prim_double_lfsr
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1148 1148 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1148 1148 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%