Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.23	100.00	100.00		85.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.73	100.00	100.00	100.00	85.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	96.96		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	96.96		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	96.96		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T69,T70,T131
1	Covered	T69,T70,T131

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T2,T8,T9

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	10	76.92
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T8,T9
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T8,T9
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Not Covered
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T168,T169,T170
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T3,T5
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T69,T70,T71
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T1,T3,T5
CheckFailError	317	Covered	T69,T70,T131
FsmStateError	289	Covered	T2,T8,T9
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T9,T6,T13
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T1,T3,T5
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T69,T70,T131
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T2,T8,T9
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T1,T3,T5
NoError->CheckFailError	317	Covered	T69,T70,T131
NoError->FsmStateError	289	Covered	T2,T8,T9
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T3,T9,T90
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T5
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T8,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T8,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T8,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T69,T70,T131
1	0	Covered	T69,T70,T131
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T8,T9
1	0	Covered	T2,T8,T9
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	461803720	460938686	0	0
DigestKnown_A	461803720	460938686	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	461803720	17351	0	0
ErrorKnown_A	461803720	460938686	0	0
FsmStateKnown_A	461803720	460938686	0	0
InitDoneKnown_A	461803720	460938686	0	0
InitReadLocksPartition_A	461803720	98768880	0	0
InitWriteLocksPartition_A	461803720	98768880	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	461803720	460938686	0	0
OtpCmdKnown_A	461803720	460938686	0	0
OtpErrorState_A	461803720	0	0	0
OtpReqKnown_A	461803720	460938686	0	0
OtpSizeKnown_A	461803720	460938686	0	0
OtpWdataKnown_A	461803720	460938686	0	0
ReadLockPropagation_A	461803720	191843098	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	461803720	460938686	0	0
TlulRdataKnown_A	461803720	460938686	0	0
TlulReadOnReadLock_A	461803720	7978	0	0
TlulRerrorKnown_A	461803720	460938686	0	0
TlulRvalidKnown_A	461803720	460938686	0	0
WriteLockPropagation_A	461803720	2189703	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	461803720	27321578	0	0
u_state_regs_A	461803720	460938686	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	17351	0	0
T57	18737	0	0	0
T69	12893	3130	0	0
T70	0	2385	0	0
T72	8632	0	0	0
T120	19608	0	0	0
T121	17314	0	0	0
T131	0	3230	0	0
T133	0	3068	0	0
T134	0	3262	0	0
T138	0	2276	0	0
T139	13413	0	0	0
T140	89087	0	0	0
T141	171448	0	0	0
T142	102474	0	0	0
T143	56801	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	98768880	0	0
T1	68010	901	0	0
T2	40272	27341	0	0
T3	67749	4326	0	0
T4	36237	2170	0	0
T5	716561	230	0	0
T8	18163	11041	0	0
T9	787573	30178	0	0
T10	10137	674	0	0
T11	14486	5733	0	0
T12	120210	25941	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	98768880	0	0
T1	68010	901	0	0
T2	40272	27341	0	0
T3	67749	4326	0	0
T4	36237	2170	0	0
T5	716561	230	0	0
T8	18163	11041	0	0
T9	787573	30178	0	0
T10	10137	674	0	0
T11	14486	5733	0	0
T12	120210	25941	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	191843098	0	0
T1	68010	4565	0	0
T2	40272	0	0	0
T3	67749	2420	0	0
T4	36237	0	0	0
T5	716561	623360	0	0
T8	18163	0	0	0
T9	787573	210701	0	0
T10	10137	0	0	0
T11	14486	0	0	0
T12	120210	0	0	0
T15	0	1752	0	0
T62	0	4586	0	0
T84	0	53199	0	0
T90	0	9060	0	0
T97	0	2224	0	0
T157	0	6893	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	7978	0	0
T1	68010	4	0	0
T2	40272	6	0	0
T3	67749	3	0	0
T4	36237	0	0	0
T5	716561	19	0	0
T8	18163	5	0	0
T9	787573	32	0	0
T10	10137	0	0	0
T11	14486	0	0	0
T12	120210	18	0	0
T90	0	11	0	0
T100	0	9	0	0
T101	0	6	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	2189703	0	0
T1	68010	6199	0	0
T2	40272	0	0	0
T3	67749	5852	0	0
T4	36237	0	0	0
T5	716561	0	0	0
T6	0	4156	0	0
T8	18163	0	0	0
T9	787573	60829	0	0
T10	10137	0	0	0
T11	14486	0	0	0
T12	120210	0	0	0
T92	0	21569	0	0
T93	0	1066	0	0
T94	0	892	0	0
T95	0	7279	0	0
T96	0	5085	0	0
T98	0	3378	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	27321578	0	0
T1	68010	58634	0	0
T2	40272	30236	0	0
T3	67749	56842	0	0
T4	36237	0	0	0
T5	716561	0	0	0
T6	0	16355	0	0
T8	18163	0	0	0
T9	787573	470570	0	0
T10	10137	0	0	0
T11	14486	0	0	0
T12	120210	0	0	0
T15	0	6622	0	0
T62	0	34860	0	0
T90	0	63804	0	0
T97	0	13519	0	0
T101	0	5308	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T88,T64,T132

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T12,T101,T62

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T69,T133,T134
1	Covered	T69,T133,T134

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T2,T8,T9

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T9

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T8,T9
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T4
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T2,T8,T9
IdleSt->ReadSt	236	Covered	T1,T3,T4
InitSt->ErrorSt	315	Covered	T168,T169,T170
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T11,T137,T144
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T5,T9
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T12,T101,T102
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T69,T70,T71
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T5,T9
CheckFailError	317	Covered	T69,T133,T134
FsmStateError	289	Covered	T2,T8,T9
MacroEccCorrError	221	Covered	T12,T101,T62
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T13,T16,T17
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T5,T9
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T69,T133,T134
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T8,T9
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T12,T87,T88
MacroEccCorrError->NoError	235	Covered	T101,T62,T129
NoError->AccessError	256	Covered	T1,T5,T9
NoError->CheckFailError	317	Covered	T69,T133,T134
NoError->FsmStateError	289	Covered	T2,T8,T9
NoError->MacroEccCorrError	221	Covered	T12,T101,T62

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T88,T64,T132
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T11,T137,T144
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T3,T9,T90
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T5,T9
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T12,T101,T62
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T12,T101,T102
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T8,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T8,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T8,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T69,T133,T134
1	0	Covered	T69,T133,T134
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T8,T9
1	0	Covered	T2,T8,T9
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	461803720	460938686	0	0
DigestKnown_A	461803720	460938686	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	461803720	9460	0	0
ErrorKnown_A	461803720	460938686	0	0
FsmStateKnown_A	461803720	460938686	0	0
InitDoneKnown_A	461803720	460938686	0	0
InitReadLocksPartition_A	461803720	98953122	0	0
InitWriteLocksPartition_A	461803720	98953122	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	461803720	460938686	0	0
OtpCmdKnown_A	461803720	460938686	0	0
OtpErrorState_A	461803720	75	0	0
OtpReqKnown_A	461803720	460938686	0	0
OtpSizeKnown_A	461803720	460938686	0	0
OtpWdataKnown_A	461803720	460938686	0	0
ReadLockPropagation_A	461803720	193780900	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	461803720	460938686	0	0
TlulRdataKnown_A	461803720	460938686	0	0
TlulReadOnReadLock_A	461803720	8031	0	0
TlulRerrorKnown_A	461803720	460938686	0	0
TlulRvalidKnown_A	461803720	460938686	0	0
WriteLockPropagation_A	461803720	2071919	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	461803720	26596758	0	0
u_state_regs_A	461803720	460938686	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	9460	0	0
T57	18737	0	0	0
T69	12893	3130	0	0
T72	8632	0	0	0
T120	19608	0	0	0
T121	17314	0	0	0
T133	0	3068	0	0
T134	0	3262	0	0
T139	13413	0	0	0
T140	89087	0	0	0
T141	171448	0	0	0
T142	102474	0	0	0
T143	56801	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	98953122	0	0
T1	68010	1156	0	0
T2	40272	27426	0	0
T3	67749	4564	0	0
T4	36237	2289	0	0
T5	716561	332	0	0
T8	18163	11109	0	0
T9	787573	31810	0	0
T10	10137	725	0	0
T11	14486	5774	0	0
T12	120210	26300	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	98953122	0	0
T1	68010	1156	0	0
T2	40272	27426	0	0
T3	67749	4564	0	0
T4	36237	2289	0	0
T5	716561	332	0	0
T8	18163	11109	0	0
T9	787573	31810	0	0
T10	10137	725	0	0
T11	14486	5774	0	0
T12	120210	26300	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	75	0	0
T11	14486	1	0	0
T12	120210	1	0	0
T15	13749	0	0	0
T63	14120	0	0	0
T90	74059	0	0	0
T100	47176	0	0	0
T101	71021	2	0	0
T102	106187	2	0	0
T137	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0
T148	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T157	15431	0	0	0
T158	52906	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	193780900	0	0
T1	68010	6595	0	0
T2	40272	5525	0	0
T3	67749	1648	0	0
T4	36237	0	0	0
T5	716561	624173	0	0
T8	18163	0	0	0
T9	787573	207018	0	0
T10	10137	0	0	0
T11	14486	0	0	0
T12	120210	5552	0	0
T15	0	1750	0	0
T90	0	9936	0	0
T101	0	5810	0	0
T157	0	6348	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	8031	0	0
T1	68010	4	0	0
T2	40272	6	0	0
T3	67749	0	0	0
T4	36237	0	0	0
T5	716561	23	0	0
T8	18163	10	0	0
T9	787573	34	0	0
T10	10137	0	0	0
T11	14486	0	0	0
T12	120210	23	0	0
T15	0	1	0	0
T90	0	16	0	0
T100	0	15	0	0
T101	0	9	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	2071919	0	0
T1	68010	1894	0	0
T2	40272	0	0	0
T3	67749	6830	0	0
T4	36237	0	0	0
T5	716561	0	0	0
T6	0	4156	0	0
T8	18163	0	0	0
T9	787573	69105	0	0
T10	10137	0	0	0
T11	14486	0	0	0
T12	120210	0	0	0
T85	0	4075	0	0
T90	0	4100	0	0
T91	0	105423	0	0
T92	0	15008	0	0
T93	0	1079	0	0
T98	0	2725	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	26596758	0	0
T1	68010	58413	0	0
T2	40272	0	0	0
T3	67749	53504	0	0
T4	36237	0	0	0
T5	716561	0	0	0
T6	0	34607	0	0
T8	18163	0	0	0
T9	787573	485293	0	0
T10	10137	0	0	0
T11	14486	3515	0	0
T12	120210	0	0	0
T15	0	6588	0	0
T62	0	34724	0	0
T85	0	27359	0	0
T90	0	63583	0	0
T97	0	5714	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T135,T72,T76

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T10,T102,T87

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T21,T22,T23

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T69,T70,T136
1	Covered	T69,T70,T136

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T2,T8,T9

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T9

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T2,T8,T9
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T4
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T8,T9,T10
IdleSt->ReadSt	236	Covered	T1,T3,T4
InitSt->ErrorSt	315	Covered	T167,T168,T171
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T2,T11,T63
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T1,T5,T9
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T156,T172,T173
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T69,T70,T71
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T1,T5,T9
CheckFailError	317	Covered	T69,T70,T136
FsmStateError	289	Covered	T2,T8,T9
MacroEccCorrError	221	Covered	T10,T102,T87
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T16,T17,T96
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T1,T5,T9
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T69,T70,T136
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T2,T8,T9
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T10,T87,T135
MacroEccCorrError->NoError	235	Covered	T102,T129,T174
NoError->AccessError	256	Covered	T1,T5,T9
NoError->CheckFailError	317	Covered	T69,T70,T136
NoError->FsmStateError	289	Covered	T2,T8,T9
NoError->MacroEccCorrError	221	Covered	T10,T102,T87

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T135,T72,T76
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T63,T88,T132
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T9,T90,T85
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T5,T9
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T10,T102,T87
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T156,T172,T173
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T22,T23
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T2,T8,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T8,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T2,T8,T9
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T2,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T69,T70,T136
1	0	Covered	T69,T70,T136
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T8,T9
1	0	Covered	T2,T8,T9
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	461803720	460938686	0	0
DigestKnown_A	461803720	460938686	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	461803720	14344	0	0
ErrorKnown_A	461803720	460938686	0	0
FsmStateKnown_A	461803720	460938686	0	0
InitDoneKnown_A	461803720	460938686	0	0
InitReadLocksPartition_A	461803720	99136033	0	0
InitWriteLocksPartition_A	461803720	99136033	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	461803720	460938686	0	0
OtpCmdKnown_A	461803720	460938686	0	0
OtpErrorState_A	461803720	61	0	0
OtpReqKnown_A	461803720	460938686	0	0
OtpSizeKnown_A	461803720	460938686	0	0
OtpWdataKnown_A	461803720	460938686	0	0
ReadLockPropagation_A	461803720	197639517	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	461803720	460938686	0	0
TlulRdataKnown_A	461803720	460938686	0	0
TlulReadOnReadLock_A	461803720	8449	0	0
TlulRerrorKnown_A	461803720	460938686	0	0
TlulRvalidKnown_A	461803720	460938686	0	0
WriteLockPropagation_A	461803720	1625427	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	461803720	18714156	0	0
u_state_regs_A	461803720	460938686	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	14344	0	0
T57	18737	0	0	0
T69	12893	3130	0	0
T70	0	2385	0	0
T72	8632	0	0	0
T120	19608	0	0	0
T121	17314	0	0	0
T133	0	3068	0	0
T136	0	3485	0	0
T138	0	2276	0	0
T139	13413	0	0	0
T140	89087	0	0	0
T141	171448	0	0	0
T142	102474	0	0	0
T143	56801	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	99136033	0	0
T1	68010	1411	0	0
T2	40272	27506	0	0
T3	67749	4802	0	0
T4	36237	2408	0	0
T5	716561	434	0	0
T8	18163	11177	0	0
T9	787573	33442	0	0
T10	10137	776	0	0
T11	14486	5808	0	0
T12	120210	26655	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	99136033	0	0
T1	68010	1411	0	0
T2	40272	27506	0	0
T3	67749	4802	0	0
T4	36237	2408	0	0
T5	716561	434	0	0
T8	18163	11177	0	0
T9	787573	33442	0	0
T10	10137	776	0	0
T11	14486	5808	0	0
T12	120210	26655	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	61	0	0
T6	235571	0	0	0
T7	449117	0	0	0
T59	12428	0	0	0
T62	42692	0	0	0
T63	14120	1	0	0
T84	62304	0	0	0
T85	38112	0	0	0
T86	8598	0	0	0
T88	0	1	0	0
T97	36863	0	0	0
T103	22207	0	0	0
T132	0	1	0	0
T147	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T152	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	197639517	0	0
T1	68010	3180	0	0
T2	40272	5521	0	0
T3	67749	2035	0	0
T4	36237	0	0	0
T5	716561	624225	0	0
T8	18163	0	0	0
T9	787573	190612	0	0
T10	10137	0	0	0
T11	14486	0	0	0
T12	120210	5548	0	0
T15	0	1748	0	0
T62	0	4386	0	0
T90	0	9947	0	0
T97	0	2214	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	8449	0	0
T1	68010	2	0	0
T2	40272	3	0	0
T3	67749	0	0	0
T4	36237	0	0	0
T5	716561	23	0	0
T8	18163	12	0	0
T9	787573	42	0	0
T10	10137	0	0	0
T11	14486	0	0	0
T12	120210	26	0	0
T15	0	1	0	0
T90	0	12	0	0
T100	0	3	0	0
T101	0	5	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	1625427	0	0
T9	787573	16661	0	0
T10	10137	0	0	0
T11	14486	0	0	0
T12	120210	0	0	0
T15	13749	0	0	0
T90	74059	7567	0	0
T91	0	95666	0	0
T92	0	11973	0	0
T93	0	1066	0	0
T95	0	4022	0	0
T96	0	6497	0	0
T100	47176	0	0	0
T101	71021	0	0	0
T102	106187	0	0	0
T157	15431	0	0	0
T162	0	6945	0	0
T164	0	32309	0	0
T165	0	810	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	18714156	0	0
T1	68010	58192	0	0
T2	40272	3092	0	0
T3	67749	0	0	0
T4	36237	0	0	0
T5	716561	0	0	0
T6	0	34471	0	0
T8	18163	0	0	0
T9	787573	271564	0	0
T10	10137	0	0	0
T11	14486	0	0	0
T12	120210	0	0	0
T15	0	6554	0	0
T62	0	34588	0	0
T63	0	3571	0	0
T85	0	27240	0	0
T90	0	63362	0	0
T101	0	5274	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461803720	460938686	0	0
T1	68010	66826	0	0
T2	40272	39946	0	0
T3	67749	66457	0	0
T4	36237	35692	0	0
T5	716561	716551	0	0
T8	18163	17916	0	0
T9	787573	779540	0	0
T10	10137	9894	0	0
T11	14486	14233	0	0
T12	120210	118580	0	0