Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
83.33	69.44	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

6 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
buf_err_code_cg_wrap[OtpSecret0ErrIdx]	0.00	1	100	1	64	64
buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]	83.33	1	100	1	64	64
buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]	83.33	1	100	1	64	64
buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]	83.33	1	100	1	64	64
buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]	83.33	1	100	1	64	64
buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]	83.33	1	100	1	64	64

---

Group Instance : buf_err_code_cg_wrap[OtpSecret0ErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpSecret0ErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	6	0	0.00

Variables for Group Instance buf_err_code_cg_wrap[OtpSecret0ErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	6	0	0.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	6	0	0.00

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
fsm_err	0	1	1
check_fail	0	1	1
ecc_uncorr_err	0	1	1
ecc_corr_err	0	1	1
macro_err	0	1	1
no_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	117178	1			T7	150		T6	1		T5	113
check_fail	4	1			T68	1		T69	1		T70	1
ecc_uncorr_err	80	1			T11	1		T26	16		T84	1
ecc_corr_err	228	1			T67	53		T52	47		T65	83
no_err	146634	1			T3	24		T4	265		T5	3

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	117107	1			T7	150		T6	1		T5	113
check_fail	3	1			T43	1		T44	1		T45	1
ecc_uncorr_err	134	1			T79	60		T149	1		T150	1
ecc_corr_err	270	1			T26	16		T41	43		T42	51
no_err	146491	1			T3	24		T4	265		T5	3

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	117134	1			T2	1		T7	150		T6	1
check_fail	7	1			T32	1		T33	1		T34	1
ecc_uncorr_err	120	1			T86	1		T47	1		T122	1
ecc_corr_err	53	1			T29	23		T30	27		T31	3
no_err	147128	1			T3	24		T4	265		T5	3

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	117088	1			T2	1		T7	150		T6	1
check_fail	27	1			T53	1		T54	1		T55	1
ecc_uncorr_err	118	1			T72	1		T85	1		T125	1
ecc_corr_err	277	1			T26	12		T51	63		T52	50
no_err	146795	1			T3	24		T4	265		T5	3

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	117019	1			T7	150		T6	1		T5	113
check_fail	20	1			T60	1		T61	1		T62	1
ecc_uncorr_err	200	1			T79	68		T134	1		T136	19
ecc_corr_err	105	1			T58	44		T59	61		-	-
no_err	146856	1			T3	24		T4	265		T5	3