Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6881628	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6622382

1

T1

23

T2

273

T3

242

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8027084	1			T1	1		T2	973		T3	683
values[0x0]	2099049	1			T1	44		T2	151		T3	34
values[0x1]	3377877	1			T1	44		T2	154		T3	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4511095	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8992915

1

T1

31

T2

578

T3

373

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52656	1			T2	3		T6	6		T5	6
valid_sources[0x01]	46888	1			T2	13		T6	3		T5	11
valid_sources[0x02]	48207	1			T1	4		T2	9		T6	4
valid_sources[0x03]	45598	1			T1	1		T2	11		T6	1
valid_sources[0x04]	54344	1			T1	1		T2	2		T6	3
valid_sources[0x05]	53228	1			T2	3		T6	6		T5	6
valid_sources[0x06]	47843	1			T2	4		T6	5		T5	12
valid_sources[0x07]	48034	1			T2	2		T6	11		T5	8
valid_sources[0x08]	49638	1			T1	1		T6	4		T5	12
valid_sources[0x09]	46420	1			T2	4		T6	6		T5	7
valid_sources[0x0a]	63317	1			T2	2		T6	4		T5	6
valid_sources[0x0b]	55492	1			T2	3		T6	4		T5	5
valid_sources[0x0c]	47076	1			T1	1		T6	4		T5	4
valid_sources[0x0d]	48437	1			T2	1		T6	2		T5	14
valid_sources[0x0e]	47472	1			T2	2		T6	5		T5	15
valid_sources[0x0f]	45199	1			T2	14		T6	8		T5	3
valid_sources[0x10]	59641	1			T2	3		T6	7		T5	11
valid_sources[0x11]	53588	1			T2	7		T6	5		T5	10
valid_sources[0x12]	50299	1			T1	2		T2	5		T6	13
valid_sources[0x13]	60053	1			T2	3		T6	11		T5	10
valid_sources[0x14]	50965	1			T6	11		T5	16		T12	1
valid_sources[0x15]	53962	1			T1	2		T2	1		T6	3
valid_sources[0x16]	50427	1			T2	3		T6	4		T5	6
valid_sources[0x17]	46535	1			T2	4		T6	7		T5	12
valid_sources[0x18]	51388	1			T6	3		T5	9		T12	1
valid_sources[0x19]	49679	1			T2	1		T6	7		T5	8
valid_sources[0x1a]	48636	1			T2	8		T6	5		T5	8
valid_sources[0x1b]	58543	1			T6	3		T5	4		T12	10
valid_sources[0x1c]	46835	1			T2	20		T3	757		T6	4
valid_sources[0x1d]	47282	1			T2	9		T6	11		T5	12
valid_sources[0x1e]	50576	1			T1	1		T2	4		T6	7
valid_sources[0x1f]	47235	1			T1	1		T2	2		T6	8
valid_sources[0x20]	51311	1			T1	3		T6	8		T5	9
valid_sources[0x21]	48722	1			T2	5		T6	7		T5	5
valid_sources[0x22]	49175	1			T6	4		T5	10		T11	10
valid_sources[0x23]	64669	1			T6	8		T5	8		T12	2
valid_sources[0x24]	53408	1			T2	7		T6	8		T5	8
valid_sources[0x25]	51468	1			T1	2		T2	5		T6	11
valid_sources[0x26]	46804	1			T1	3		T2	3		T6	8
valid_sources[0x27]	46581	1			T6	7		T5	8		T115	2
valid_sources[0x28]	49139	1			T2	9		T6	1		T5	2
valid_sources[0x29]	70776	1			T2	5		T6	5		T5	7
valid_sources[0x2a]	46167	1			T1	1		T2	4		T6	4
valid_sources[0x2b]	46642	1			T1	1		T2	5		T6	4
valid_sources[0x2c]	48514	1			T2	14		T6	8		T5	8
valid_sources[0x2d]	52246	1			T2	9		T6	3		T5	9
valid_sources[0x2e]	50112	1			T2	12		T6	6		T5	12
valid_sources[0x2f]	45394	1			T1	1		T5	8		T11	8
valid_sources[0x30]	80140	1			T1	1		T2	3		T6	10
valid_sources[0x31]	57887	1			T2	5		T6	4		T5	5
valid_sources[0x32]	45464	1			T2	8		T6	7		T5	11
valid_sources[0x33]	48513	1			T2	8		T6	8		T5	9
valid_sources[0x34]	51833	1			T1	1		T2	1		T6	11
valid_sources[0x35]	46248	1			T6	5		T5	8		T11	1
valid_sources[0x36]	57842	1			T6	5		T5	15		T12	2
valid_sources[0x37]	50091	1			T2	8		T6	4		T5	8
valid_sources[0x38]	46488	1			T2	1		T6	11		T5	9
valid_sources[0x39]	49504	1			T2	5		T6	7		T5	6
valid_sources[0x3a]	53130	1			T6	3		T5	13		T12	11
valid_sources[0x3b]	45516	1			T2	7		T6	4		T5	4
valid_sources[0x3c]	51873	1			T6	8		T5	12		T12	2
valid_sources[0x3d]	102232	1			T2	20		T6	5		T5	6
valid_sources[0x3e]	65806	1			T6	7		T5	13		T12	6
valid_sources[0x3f]	49650	1			T2	16		T6	4		T5	7
valid_sources[0x40]	46089	1			T2	7		T6	4		T5	9
valid_sources[0x41]	46980	1			T1	1		T6	1		T5	6
valid_sources[0x42]	46916	1			T1	2		T2	2		T6	1
valid_sources[0x43]	59400	1			T2	2		T6	5		T5	10
valid_sources[0x44]	48890	1			T6	12		T5	10		T12	15
valid_sources[0x45]	59599	1			T6	4		T5	8		T11	7
valid_sources[0x46]	51018	1			T2	3		T6	9		T5	10
valid_sources[0x47]	56006	1			T1	1		T2	24		T6	6
valid_sources[0x48]	97292	1			T6	2		T5	11		T12	2
valid_sources[0x49]	49798	1			T2	8		T6	8		T5	6
valid_sources[0x4a]	44857	1			T1	1		T2	6		T6	8
valid_sources[0x4b]	52065	1			T6	11		T5	11		T12	5
valid_sources[0x4c]	47108	1			T2	13		T6	6		T5	3
valid_sources[0x4d]	46107	1			T6	5		T5	1		T12	5
valid_sources[0x4e]	46360	1			T2	2		T6	3		T5	7
valid_sources[0x4f]	48976	1			T2	3		T6	6		T5	11
valid_sources[0x50]	104192	1			T2	5		T6	8		T5	10
valid_sources[0x51]	48213	1			T6	7		T5	6		T12	1
valid_sources[0x52]	51799	1			T2	2		T6	6		T5	8
valid_sources[0x53]	60550	1			T6	6		T5	4		T11	1
valid_sources[0x54]	48060	1			T2	4		T6	8		T5	12
valid_sources[0x55]	53853	1			T2	8		T5	9		T12	4
valid_sources[0x56]	56876	1			T6	6		T5	6		T13	1
valid_sources[0x57]	45478	1			T2	3		T6	1		T5	17
valid_sources[0x58]	51201	1			T2	1		T6	10		T5	9
valid_sources[0x59]	61797	1			T2	3		T6	4		T5	10
valid_sources[0x5a]	46510	1			T6	4		T5	18		T12	1
valid_sources[0x5b]	55213	1			T1	3		T2	6		T6	4
valid_sources[0x5c]	50384	1			T1	1		T2	7		T6	3
valid_sources[0x5d]	51914	1			T2	7		T6	8		T5	10
valid_sources[0x5e]	50837	1			T1	2		T6	10		T5	8
valid_sources[0x5f]	59134	1			T6	6		T5	11		T11	6
valid_sources[0x60]	47503	1			T1	1		T2	9		T6	6
valid_sources[0x61]	46877	1			T2	4		T6	2		T5	9
valid_sources[0x62]	46683	1			T2	1		T6	6		T5	9
valid_sources[0x63]	48876	1			T2	3		T6	8		T5	8
valid_sources[0x64]	46387	1			T2	4		T6	6		T5	10
valid_sources[0x65]	47517	1			T1	1		T6	7		T5	7
valid_sources[0x66]	60297	1			T2	6		T6	6		T5	8
valid_sources[0x67]	47359	1			T6	8		T5	3		T12	1
valid_sources[0x68]	51044	1			T2	11		T6	2		T5	13
valid_sources[0x69]	47022	1			T2	8		T6	8		T5	8
valid_sources[0x6a]	49740	1			T6	2		T5	4		T12	3
valid_sources[0x6b]	45845	1			T2	5		T6	3		T5	11
valid_sources[0x6c]	51862	1			T1	2		T6	4		T5	10
valid_sources[0x6d]	51460	1			T1	1		T2	5		T6	3
valid_sources[0x6e]	58368	1			T2	7		T6	7		T5	2
valid_sources[0x6f]	143407	1			T6	7		T5	11		T13	14
valid_sources[0x70]	48599	1			T2	4		T6	4		T5	18
valid_sources[0x71]	45698	1			T2	13		T6	19		T5	6
valid_sources[0x72]	48025	1			T2	6		T6	4		T5	6
valid_sources[0x73]	48609	1			T2	1		T6	5		T5	7
valid_sources[0x74]	45272	1			T2	8		T6	5		T5	9
valid_sources[0x75]	55448	1			T2	6		T6	5		T5	11
valid_sources[0x76]	48112	1			T6	13		T5	11		T115	2
valid_sources[0x77]	53094	1			T2	6		T6	6		T5	13
valid_sources[0x78]	45159	1			T2	9		T6	4		T5	14
valid_sources[0x79]	52101	1			T1	1		T2	6		T6	1
valid_sources[0x7a]	44232	1			T2	10		T6	4		T5	8
valid_sources[0x7b]	49790	1			T1	1		T2	8		T6	4
valid_sources[0x7c]	45848	1			T2	3		T6	7		T5	6
valid_sources[0x7d]	46189	1			T1	1		T2	3		T6	8
valid_sources[0x7e]	49893	1			T6	3		T5	12		T11	3
valid_sources[0x7f]	52476	1			T1	3		T2	7		T6	5
valid_sources[0x80]	57385	1			T2	3		T6	3		T5	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3260919

1

T1

1

T2

139

T3

213

values[0x0]

all_enables

biggest_size

1719862

1

T1

14

T2

77

T3

16

values[0x1]

all_enables

biggest_size

1641601

1

T1

8

T2

57

T3

13

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	220996	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7968381

1

T3

20

T7

160

T4

180

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2043369	1			T3	10		T7	80		T4	90
values[0x0]	2984773	1			T3	5		T7	40		T4	47
values[0x1]	3161235	1			T3	5		T7	40		T4	43

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	80193	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

8109184

1

T3

20

T7

160

T4

180

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	33075	1			T9	634		T10	320		T14	281
valid_sources[0x01]	31147	1			T7	2		T4	1		T5	2
valid_sources[0x02]	32904	1			T4	2		T9	639		T10	318
valid_sources[0x03]	32378	1			T9	633		T10	324		T14	267
valid_sources[0x04]	31115	1			T9	606		T10	320		T14	322
valid_sources[0x05]	32771	1			T9	654		T10	318		T14	315
valid_sources[0x06]	32697	1			T4	2		T5	3		T9	669
valid_sources[0x07]	32787	1			T9	619		T10	354		T14	282
valid_sources[0x08]	31894	1			T9	678		T10	326		T14	293
valid_sources[0x09]	34584	1			T4	1		T9	643		T10	334
valid_sources[0x0a]	31788	1			T4	1		T9	657		T10	317
valid_sources[0x0b]	31498	1			T7	1		T9	598		T10	365
valid_sources[0x0c]	33631	1			T4	3		T9	632		T116	35
valid_sources[0x0d]	32141	1			T9	655		T10	302		T14	361
valid_sources[0x0e]	34448	1			T9	661		T10	315		T14	260
valid_sources[0x0f]	31895	1			T4	6		T9	637		T10	363
valid_sources[0x10]	31869	1			T7	1		T4	3		T9	618
valid_sources[0x11]	33066	1			T7	1		T5	4		T9	666
valid_sources[0x12]	32853	1			T9	702		T10	317		T14	243
valid_sources[0x13]	34316	1			T9	668		T10	334		T14	255
valid_sources[0x14]	31016	1			T7	2		T4	4		T9	552
valid_sources[0x15]	31634	1			T7	1		T4	2		T9	625
valid_sources[0x16]	32459	1			T7	1		T4	3		T9	657
valid_sources[0x17]	32704	1			T4	3		T5	3		T9	666
valid_sources[0x18]	31244	1			T7	1		T9	602		T10	324
valid_sources[0x19]	30428	1			T9	616		T10	347		T14	340
valid_sources[0x1a]	33414	1			T7	1		T9	589		T10	351
valid_sources[0x1b]	30151	1			T4	2		T9	649		T10	317
valid_sources[0x1c]	29804	1			T4	1		T9	641		T10	341
valid_sources[0x1d]	33182	1			T7	5		T5	1		T9	631
valid_sources[0x1e]	31637	1			T4	2		T5	1		T9	648
valid_sources[0x1f]	31865	1			T9	650		T10	332		T14	259
valid_sources[0x20]	31431	1			T7	1		T4	1		T9	647
valid_sources[0x21]	31969	1			T7	1		T9	627		T10	328
valid_sources[0x22]	31964	1			T7	1		T4	1		T9	577
valid_sources[0x23]	31436	1			T9	623		T10	347		T14	258
valid_sources[0x24]	30587	1			T9	654		T10	313		T14	260
valid_sources[0x25]	30869	1			T7	1		T9	669		T10	308
valid_sources[0x26]	31849	1			T4	1		T9	675		T10	299
valid_sources[0x27]	32269	1			T5	11		T9	590		T10	319
valid_sources[0x28]	33589	1			T9	648		T10	309		T14	352
valid_sources[0x29]	33387	1			T5	1		T9	663		T10	317
valid_sources[0x2a]	32462	1			T4	6		T9	656		T10	346
valid_sources[0x2b]	33242	1			T9	626		T10	312		T14	258
valid_sources[0x2c]	31401	1			T9	637		T10	354		T14	245
valid_sources[0x2d]	32081	1			T7	1		T5	1		T9	612
valid_sources[0x2e]	31804	1			T9	655		T10	344		T14	230
valid_sources[0x2f]	32038	1			T7	1		T9	633		T10	339
valid_sources[0x30]	31435	1			T7	1		T4	1		T9	612
valid_sources[0x31]	31028	1			T7	2		T9	614		T10	288
valid_sources[0x32]	32778	1			T7	1		T5	1		T9	634
valid_sources[0x33]	32488	1			T7	1		T9	622		T10	316
valid_sources[0x34]	31271	1			T7	3		T4	2		T9	688
valid_sources[0x35]	31552	1			T7	1		T4	1		T9	683
valid_sources[0x36]	33758	1			T5	10		T9	650		T10	345
valid_sources[0x37]	30941	1			T9	656		T10	363		T14	298
valid_sources[0x38]	34544	1			T4	1		T9	675		T10	319
valid_sources[0x39]	32514	1			T7	2		T9	639		T10	314
valid_sources[0x3a]	33341	1			T9	662		T10	299		T14	253
valid_sources[0x3b]	33352	1			T7	1		T9	631		T10	321
valid_sources[0x3c]	32806	1			T9	607		T10	332		T14	285
valid_sources[0x3d]	31983	1			T9	627		T10	338		T14	298
valid_sources[0x3e]	32412	1			T7	1		T9	608		T10	331
valid_sources[0x3f]	31976	1			T9	662		T10	352		T14	340
valid_sources[0x40]	30744	1			T7	1		T4	1		T9	671
valid_sources[0x41]	32305	1			T9	638		T10	324		T14	276
valid_sources[0x42]	30422	1			T9	712		T10	320		T14	304
valid_sources[0x43]	31708	1			T7	2		T4	1		T5	3
valid_sources[0x44]	31524	1			T9	668		T10	309		T14	277
valid_sources[0x45]	31423	1			T4	4		T5	4		T9	623
valid_sources[0x46]	31863	1			T4	12		T9	641		T10	318
valid_sources[0x47]	31976	1			T9	658		T10	326		T14	306
valid_sources[0x48]	32300	1			T7	2		T9	614		T10	343
valid_sources[0x49]	32561	1			T7	2		T9	641		T10	352
valid_sources[0x4a]	31018	1			T3	20		T4	3		T9	696
valid_sources[0x4b]	31899	1			T4	4		T9	674		T10	336
valid_sources[0x4c]	31789	1			T7	1		T9	586		T10	325
valid_sources[0x4d]	32945	1			T7	2		T9	615		T10	338
valid_sources[0x4e]	32097	1			T7	1		T9	662		T10	349
valid_sources[0x4f]	30193	1			T4	2		T9	701		T10	327
valid_sources[0x50]	32698	1			T4	1		T9	594		T10	350
valid_sources[0x51]	31560	1			T9	642		T10	313		T14	304
valid_sources[0x52]	31584	1			T7	1		T9	598		T10	314
valid_sources[0x53]	32267	1			T9	628		T10	329		T14	359
valid_sources[0x54]	33242	1			T7	1		T9	617		T10	320
valid_sources[0x55]	31748	1			T7	1		T4	1		T9	662
valid_sources[0x56]	33348	1			T5	2		T9	631		T10	327
valid_sources[0x57]	32641	1			T9	674		T10	341		T14	266
valid_sources[0x58]	32141	1			T7	2		T4	2		T9	651
valid_sources[0x59]	32618	1			T9	654		T10	318		T14	315
valid_sources[0x5a]	33117	1			T4	3		T9	639		T10	347
valid_sources[0x5b]	31399	1			T9	567		T10	317		T14	243
valid_sources[0x5c]	30903	1			T4	2		T9	690		T10	331
valid_sources[0x5d]	29577	1			T7	1		T9	654		T10	337
valid_sources[0x5e]	31351	1			T7	2		T4	4		T9	530
valid_sources[0x5f]	31602	1			T7	1		T9	647		T10	341
valid_sources[0x60]	32461	1			T4	2		T9	676		T10	351
valid_sources[0x61]	31641	1			T7	2		T5	2		T9	671
valid_sources[0x62]	31095	1			T4	4		T9	649		T10	327
valid_sources[0x63]	32510	1			T7	1		T5	2		T9	627
valid_sources[0x64]	33040	1			T9	620		T10	350		T14	265
valid_sources[0x65]	32125	1			T9	660		T10	270		T14	328
valid_sources[0x66]	31216	1			T9	586		T10	314		T14	242
valid_sources[0x67]	32406	1			T7	3		T9	651		T10	330
valid_sources[0x68]	31880	1			T5	4		T9	641		T10	313
valid_sources[0x69]	31880	1			T9	737		T10	333		T14	285
valid_sources[0x6a]	33178	1			T9	648		T10	314		T14	306
valid_sources[0x6b]	30486	1			T7	1		T9	645		T10	296
valid_sources[0x6c]	32839	1			T7	1		T5	1		T9	630
valid_sources[0x6d]	31510	1			T9	661		T10	338		T14	294
valid_sources[0x6e]	33690	1			T7	1		T9	617		T10	333
valid_sources[0x6f]	32967	1			T9	663		T10	341		T14	253
valid_sources[0x70]	30879	1			T9	595		T10	358		T14	249
valid_sources[0x71]	32963	1			T7	1		T4	5		T9	630
valid_sources[0x72]	31142	1			T4	3		T9	629		T10	316
valid_sources[0x73]	32660	1			T9	643		T10	309		T14	277
valid_sources[0x74]	29819	1			T7	1		T5	1		T9	601
valid_sources[0x75]	32144	1			T5	4		T9	631		T10	302
valid_sources[0x76]	33608	1			T9	710		T10	324		T14	308
valid_sources[0x77]	32886	1			T4	1		T5	3		T9	659
valid_sources[0x78]	29713	1			T4	1		T9	678		T10	312
valid_sources[0x79]	31202	1			T5	6		T13	20		T9	682
valid_sources[0x7a]	30707	1			T7	1		T4	2		T9	654
valid_sources[0x7b]	31747	1			T9	555		T10	327		T14	339
valid_sources[0x7c]	30399	1			T7	1		T4	1		T9	604
valid_sources[0x7d]	32140	1			T7	1		T4	2		T9	602
valid_sources[0x7e]	30852	1			T9	701		T10	316		T14	264
valid_sources[0x7f]	32531	1			T9	627		T10	332		T14	263
valid_sources[0x80]	32438	1			T7	2		T4	1		T9	652

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2029708

1

T3

10

T7

80

T4

90

values[0x0]

all_enables

biggest_size

2969995

1

T3

5

T7

40

T4

47

values[0x1]

all_enables

biggest_size

2968678

1

T3

5

T7

40

T4

43