Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

22820450

1

T1

66

T2

1005

T3

515

full_word

7583865

1

T1

23

T2

273

T3

242

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30403985	1			T1	89		T2	1278		T3	757
auto[TlIntgErrCmd]	112	1			T275	2		T276	4		T277	7
auto[TlIntgErrData]	113	1			T275	4		T276	2		T277	7
auto[TlIntgErrBoth]	105	1			T275	4		T276	4		T277	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9198985

1

T1

1

T2

973

T3

683

auto[1]

21205330

1

T1

88

T2

305

T3

74

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5819983	1			T2	834		T3	470		T7	1312
auto[TlIntgErrNone]	partial	auto[1]	17000163	1			T1	66		T2	171		T3	45
auto[TlIntgErrNone]	full_word	auto[0]	3378861	1			T1	1		T2	139		T3	213
auto[TlIntgErrNone]	full_word	auto[1]	4204978	1			T1	22		T2	134		T3	29
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T275	2		T276	2		T277	1
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T276	1		T277	4		T284	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T284	1		T357	1		T283	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T276	1		T277	2		T358	1
auto[TlIntgErrData]	partial	auto[0]	51	1			T275	1		T277	4		T284	3
auto[TlIntgErrData]	partial	auto[1]	48	1			T275	1		T276	2		T277	2
auto[TlIntgErrData]	full_word	auto[0]	9	1			T275	2		T359	1		T360	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T277	1		T361	1		T357	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T275	2		T276	2		T277	5
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T275	2		T276	2		T277	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T284	2		T362	1		-	-