Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.21	94.16	96.15	97.12		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	421975324	7179334	0	0
check_regwen_rd_A	421975324	3304	0	0
check_timeout_rd_A	421975324	2932	0	0
check_trigger_regwen_rd_A	421975324	2970	0	0
consistency_check_period_rd_A	421975324	3175	0	0
creator_sw_cfg_read_lock_rd_A	421975324	2772	0	0
direct_access_address_rd_A	421975324	2100	0	0
direct_access_wdata_0_rd_A	421975324	1254	0	0
direct_access_wdata_1_rd_A	421975324	1601	0	0
integrity_check_period_rd_A	421975324	2991	0	0
intr_enable_rd_A	421975324	4043	0	0
owner_sw_cfg_read_lock_rd_A	421975324	2736	0	0
rot_creator_auth_codesign_read_lock_rd_A	421975324	2606	0	0
rot_creator_auth_state_read_lock_rd_A	421975324	2600	0	0
vendor_test_read_lock_rd_A	421975324	2655	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421975324	7179334	0	0
T9	552962	145842	0	0
T10	372579	75357	0	0
T14	265135	62195	0	0
T16	0	42371	0	0
T17	0	102001	0	0
T25	0	55724	0	0
T26	48213	0	0	0
T38	0	81322	0	0
T39	0	70639	0	0
T46	11483	0	0	0
T49	0	82327	0	0
T53	16335	0	0	0
T71	15711	0	0	0
T72	11802	0	0	0
T116	80278	0	0	0
T181	11699	0	0	0
T262	0	23516	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421975324	3304	0	0
T10	372579	81	0	0
T14	265135	0	0	0
T17	0	66	0	0
T18	0	170	0	0
T25	0	27	0	0
T38	0	84	0	0
T40	67967	0	0	0
T46	11483	0	0	0
T53	16335	0	0	0
T71	15711	0	0	0
T72	11802	0	0	0
T154	0	191	0	0
T155	0	102	0	0
T177	29869	0	0	0
T181	11699	0	0	0
T204	17573	0	0	0
T288	0	47	0	0
T346	0	68	0	0
T347	0	20	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421975324	2932	0	0
T10	372579	61	0	0
T14	265135	0	0	0
T17	0	123	0	0
T18	0	175	0	0
T25	0	26	0	0
T38	0	112	0	0
T40	67967	0	0	0
T46	11483	0	0	0
T53	16335	0	0	0
T71	15711	0	0	0
T72	11802	0	0	0
T154	0	159	0	0
T155	0	128	0	0
T177	29869	0	0	0
T181	11699	0	0	0
T204	17573	0	0	0
T288	0	40	0	0
T346	0	65	0	0
T347	0	26	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421975324	2970	0	0
T10	372579	49	0	0
T14	265135	0	0	0
T17	0	51	0	0
T18	0	157	0	0
T25	0	43	0	0
T38	0	66	0	0
T40	67967	0	0	0
T46	11483	0	0	0
T53	16335	0	0	0
T71	15711	0	0	0
T72	11802	0	0	0
T154	0	172	0	0
T155	0	81	0	0
T177	29869	0	0	0
T181	11699	0	0	0
T204	17573	0	0	0
T288	0	41	0	0
T346	0	27	0	0
T347	0	23	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421975324	3175	0	0
T10	372579	60	0	0
T14	265135	0	0	0
T17	0	50	0	0
T18	0	148	0	0
T25	0	23	0	0
T38	0	107	0	0
T40	67967	0	0	0
T46	11483	0	0	0
T53	16335	0	0	0
T71	15711	0	0	0
T72	11802	0	0	0
T154	0	151	0	0
T155	0	101	0	0
T177	29869	0	0	0
T181	11699	0	0	0
T204	17573	0	0	0
T288	0	84	0	0
T346	0	55	0	0
T347	0	25	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421975324	2772	0	0
T10	372579	58	0	0
T14	265135	0	0	0
T17	0	76	0	0
T18	0	188	0	0
T25	0	31	0	0
T38	0	129	0	0
T40	67967	0	0	0
T46	11483	0	0	0
T53	16335	0	0	0
T71	15711	0	0	0
T72	11802	0	0	0
T154	0	151	0	0
T155	0	99	0	0
T177	29869	0	0	0
T181	11699	0	0	0
T204	17573	0	0	0
T288	0	78	0	0
T346	0	93	0	0
T347	0	20	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421975324	2100	0	0
T10	372579	48	0	0
T14	265135	0	0	0
T17	0	83	0	0
T18	0	115	0	0
T25	0	58	0	0
T38	0	56	0	0
T40	67967	0	0	0
T46	11483	0	0	0
T53	16335	0	0	0
T71	15711	0	0	0
T72	11802	0	0	0
T154	0	194	0	0
T155	0	118	0	0
T177	29869	0	0	0
T181	11699	0	0	0
T204	17573	0	0	0
T288	0	74	0	0
T346	0	52	0	0
T347	0	54	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421975324	1254	0	0
T10	372579	62	0	0
T14	265135	0	0	0
T17	0	51	0	0
T18	0	129	0	0
T25	0	13	0	0
T38	0	95	0	0
T40	67967	0	0	0
T46	11483	0	0	0
T53	16335	0	0	0
T71	15711	0	0	0
T72	11802	0	0	0
T154	0	132	0	0
T155	0	54	0	0
T177	29869	0	0	0
T181	11699	0	0	0
T204	17573	0	0	0
T288	0	31	0	0
T346	0	33	0	0
T347	0	24	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421975324	1601	0	0
T10	372579	37	0	0
T14	265135	0	0	0
T17	0	56	0	0
T18	0	142	0	0
T25	0	32	0	0
T38	0	110	0	0
T40	67967	0	0	0
T46	11483	0	0	0
T53	16335	0	0	0
T71	15711	0	0	0
T72	11802	0	0	0
T154	0	200	0	0
T155	0	72	0	0
T177	29869	0	0	0
T181	11699	0	0	0
T204	17573	0	0	0
T288	0	52	0	0
T346	0	23	0	0
T347	0	29	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421975324	2991	0	0
T10	372579	29	0	0
T14	265135	0	0	0
T17	0	67	0	0
T18	0	86	0	0
T25	0	29	0	0
T38	0	72	0	0
T40	67967	0	0	0
T46	11483	0	0	0
T53	16335	0	0	0
T71	15711	0	0	0
T72	11802	0	0	0
T154	0	150	0	0
T155	0	81	0	0
T177	29869	0	0	0
T181	11699	0	0	0
T204	17573	0	0	0
T288	0	50	0	0
T346	0	79	0	0
T347	0	25	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421975324	4043	0	0
T10	372579	40	0	0
T14	265135	0	0	0
T17	0	49	0	0
T18	0	142	0	0
T25	0	24	0	0
T38	0	131	0	0
T40	67967	0	0	0
T46	11483	0	0	0
T53	16335	0	0	0
T71	15711	0	0	0
T72	11802	0	0	0
T114	0	40	0	0
T139	0	9	0	0
T141	0	10	0	0
T155	0	102	0	0
T177	29869	0	0	0
T181	11699	0	0	0
T204	17573	0	0	0
T346	0	52	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421975324	2736	0	0
T10	372579	47	0	0
T14	265135	0	0	0
T17	0	65	0	0
T18	0	167	0	0
T25	0	21	0	0
T38	0	83	0	0
T40	67967	0	0	0
T46	11483	0	0	0
T53	16335	0	0	0
T71	15711	0	0	0
T72	11802	0	0	0
T154	0	179	0	0
T155	0	67	0	0
T177	29869	0	0	0
T181	11699	0	0	0
T204	17573	0	0	0
T288	0	93	0	0
T346	0	39	0	0
T347	0	19	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421975324	2606	0	0
T10	372579	64	0	0
T14	265135	0	0	0
T17	0	47	0	0
T18	0	156	0	0
T25	0	22	0	0
T38	0	70	0	0
T40	67967	0	0	0
T46	11483	0	0	0
T53	16335	0	0	0
T71	15711	0	0	0
T72	11802	0	0	0
T154	0	203	0	0
T155	0	100	0	0
T177	29869	0	0	0
T181	11699	0	0	0
T204	17573	0	0	0
T288	0	49	0	0
T346	0	35	0	0
T347	0	32	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421975324	2600	0	0
T10	372579	35	0	0
T14	265135	0	0	0
T17	0	94	0	0
T18	0	197	0	0
T25	0	21	0	0
T38	0	72	0	0
T40	67967	0	0	0
T46	11483	0	0	0
T53	16335	0	0	0
T71	15711	0	0	0
T72	11802	0	0	0
T154	0	167	0	0
T155	0	122	0	0
T177	29869	0	0	0
T181	11699	0	0	0
T204	17573	0	0	0
T288	0	55	0	0
T346	0	61	0	0
T347	0	32	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	421975324	2655	0	0
T10	372579	68	0	0
T14	265135	0	0	0
T17	0	126	0	0
T18	0	178	0	0
T25	0	15	0	0
T38	0	96	0	0
T40	67967	0	0	0
T46	11483	0	0	0
T53	16335	0	0	0
T71	15711	0	0	0
T72	11802	0	0	0
T154	0	137	0	0
T155	0	92	0	0
T177	29869	0	0	0
T181	11699	0	0	0
T204	17573	0	0	0
T288	0	51	0	0
T346	0	47	0	0
T347	0	12	0	0