Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf
| Line No. | Total | Covered | Percent |
TOTAL | | 91 | 91 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
ALWAYS | 164 | 68 | 68 | 100.00 |
CONT_ASSIGN | 334 | 1 | 1 | 100.00 |
CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 342 | 1 | 1 | 100.00 |
CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
CONT_ASSIGN | 350 | 1 | 1 | 100.00 |
CONT_ASSIGN | 354 | 1 | 1 | 100.00 |
CONT_ASSIGN | 358 | 1 | 1 | 100.00 |
CONT_ASSIGN | 395 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 454 | 1 | 1 | 100.00 |
ALWAYS | 461 | 3 | 3 | 100.00 |
ALWAYS | 464 | 8 | 8 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
138 |
1 |
1 |
149 |
1 |
1 |
164 |
1 |
1 |
167 |
1 |
1 |
170 |
1 |
1 |
171 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
179 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
186 |
1 |
1 |
191 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
196 |
|
unreachable |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
|
|
|
MISSING_ELSE |
215 |
1 |
1 |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
|
|
|
MISSING_ELSE |
224 |
1 |
1 |
225 |
1 |
1 |
|
|
|
MISSING_ELSE |
233 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
236 |
1 |
1 |
237 |
1 |
1 |
|
|
|
MISSING_ELSE |
246 |
1 |
1 |
248 |
1 |
1 |
249 |
1 |
1 |
250 |
1 |
1 |
251 |
1 |
1 |
252 |
1 |
1 |
|
|
|
MISSING_ELSE |
255 |
1 |
1 |
256 |
1 |
1 |
257 |
1 |
1 |
258 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
268 |
1 |
1 |
269 |
1 |
1 |
270 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
|
|
|
MISSING_ELSE |
276 |
1 |
1 |
277 |
1 |
1 |
279 |
1 |
1 |
|
|
|
MISSING_ELSE |
288 |
1 |
1 |
289 |
1 |
1 |
|
|
|
MISSING_ELSE |
293 |
1 |
1 |
294 |
1 |
1 |
295 |
1 |
1 |
296 |
1 |
1 |
297 |
1 |
1 |
298 |
1 |
1 |
|
|
|
MISSING_ELSE |
314 |
1 |
1 |
315 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
321 |
1 |
1 |
322 |
1 |
1 |
323 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
334 |
1 |
1 |
336 |
1 |
1 |
342 |
1 |
1 |
349 |
1 |
1 |
350 |
1 |
1 |
354 |
1 |
1 |
358 |
1 |
1 |
395 |
1 |
1 |
420 |
1 |
1 |
454 |
1 |
1 |
461 |
3 |
3 |
464 |
1 |
1 |
465 |
1 |
1 |
466 |
1 |
1 |
467 |
1 |
1 |
469 |
1 |
1 |
470 |
1 |
1 |
471 |
1 |
1 |
472 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 220
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T73,T47,T182 |
LINE 272
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T3,T6 |
1 | Covered | T110,T67,T174 |
LINE 288
EXPRESSION (error_q == NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T7,T6 |
1 | Covered | T19,T20,T21 |
LINE 316
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T82 |
1 | Covered | T82 |
LINE 324
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T7,T6 |
1 | Covered | T2,T7,T5 |
LINE 336
EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T6 |
LINE 336
SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T7,T4,T5 |
1 | 1 | Covered | T2,T3,T6 |
LINE 336
SUB-EXPRESSION (tlul_rerror_o == '0)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 342
EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
--------------------1------------------- ------------------2------------------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T2,T3,T7 |
LINE 349
EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
---------------1---------------
-1- | Status | Tests |
0 | Covered | T2,T3,T6 |
1 | Covered | T1,T2,T3 |
LINE 349
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 358
EXPRESSION
Number Term
1 (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1- | Status | Tests |
0 | Covered | T2,T3,T6 |
1 | Covered | T1,T2,T3 |
LINE 358
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 395
EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 420
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T4,T5 |
LINE 420
SUB-EXPRESSION (digest_o != '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T4,T5 |
FSM Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
7 |
7 |
100.00 |
(Not included in score) |
Transitions |
13 |
12 |
92.31 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
ErrorSt |
224 |
Covered |
T2,T7,T6 |
IdleSt |
196 |
Covered |
T1,T2,T3 |
InitSt |
194 |
Covered |
T1,T2,T3 |
InitWaitSt |
207 |
Covered |
T1,T2,T3 |
ReadSt |
236 |
Covered |
T2,T3,T6 |
ReadWaitSt |
252 |
Covered |
T2,T3,T6 |
ResetSt |
190 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests | Exclude Annotation |
IdleSt->ErrorSt |
315 |
Covered |
T7,T5,T11 |
|
IdleSt->ReadSt |
236 |
Covered |
T2,T3,T6 |
|
InitSt->ErrorSt |
315 |
Covered |
T12,T118,T129 |
|
InitSt->InitWaitSt |
207 |
Covered |
T1,T2,T3 |
|
InitWaitSt->ErrorSt |
224 |
Covered |
T2,T6,T115 |
|
InitWaitSt->IdleSt |
218 |
Covered |
T1,T2,T3 |
|
ReadSt->ErrorSt |
315 |
Not Covered |
|
|
ReadSt->IdleSt |
255 |
Covered |
T4,T9,T116 |
|
ReadSt->ReadWaitSt |
252 |
Covered |
T2,T3,T6 |
|
ReadWaitSt->ErrorSt |
276 |
Covered |
T174,T175,T223 |
|
ReadWaitSt->IdleSt |
270 |
Covered |
T2,T3,T6 |
|
ResetSt->ErrorSt |
315 |
Covered |
T80,T81,T82 |
|
ResetSt->IdleSt |
196 |
Excluded |
|
VC_COV_UNR |
ResetSt->InitSt |
194 |
Covered |
T1,T2,T3 |
|
Summary for FSM :: error_q
| Total | Covered | Percent | |
States |
5 |
5 |
100.00 |
(Not included in score) |
Transitions |
11 |
10 |
90.91 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: error_q
states | Line No. | Covered | Tests |
AccessError |
256 |
Covered |
T4,T9,T116 |
CheckFailError |
317 |
Covered |
T82 |
FsmStateError |
289 |
Covered |
T2,T7,T5 |
MacroEccCorrError |
221 |
Covered |
T73,T110,T67 |
NoError |
235 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests | Exclude Annotation |
AccessError->CheckFailError |
317 |
Excluded |
|
VC_COV_UNR |
AccessError->FsmStateError |
325 |
Covered |
T9,T116,T128 |
|
AccessError->MacroEccCorrError |
221 |
Excluded |
|
VC_COV_UNR |
AccessError->NoError |
235 |
Covered |
T4,T9,T116 |
|
CheckFailError->AccessError |
256 |
Excluded |
|
VC_COV_UNR |
CheckFailError->FsmStateError |
325 |
Excluded |
|
VC_COV_UNR |
CheckFailError->MacroEccCorrError |
221 |
Excluded |
|
VC_COV_UNR |
CheckFailError->NoError |
235 |
Covered |
T82 |
|
FsmStateError->AccessError |
256 |
Excluded |
|
VC_COV_UNR |
FsmStateError->CheckFailError |
317 |
Excluded |
|
VC_COV_UNR |
FsmStateError->MacroEccCorrError |
221 |
Excluded |
|
VC_COV_UNR |
FsmStateError->NoError |
235 |
Covered |
T2,T7,T5 |
|
MacroEccCorrError->AccessError |
256 |
Excluded |
|
VC_COV_UNR |
MacroEccCorrError->CheckFailError |
317 |
Not Covered |
|
|
MacroEccCorrError->FsmStateError |
325 |
Covered |
T73,T174,T224 |
|
MacroEccCorrError->NoError |
235 |
Covered |
T110,T67,T76 |
|
NoError->AccessError |
256 |
Covered |
T4,T9,T116 |
|
NoError->CheckFailError |
317 |
Covered |
T82 |
|
NoError->FsmStateError |
289 |
Covered |
T2,T7,T5 |
|
NoError->MacroEccCorrError |
221 |
Covered |
T73,T110,T67 |
|
Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf
| Line No. | Total | Covered | Percent |
Branches |
|
44 |
44 |
100.00 |
TERNARY |
336 |
2 |
2 |
100.00 |
TERNARY |
349 |
2 |
2 |
100.00 |
TERNARY |
358 |
2 |
2 |
100.00 |
TERNARY |
395 |
2 |
2 |
100.00 |
TERNARY |
420 |
2 |
2 |
100.00 |
CASE |
186 |
23 |
23 |
100.00 |
IF |
314 |
3 |
3 |
100.00 |
IF |
321 |
3 |
3 |
100.00 |
IF |
461 |
2 |
2 |
100.00 |
IF |
464 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 336 ((tlul_rvalid_o && (tlul_rerror_o == '0))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 349 ((otp_addr_sel == DigestAddrSel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T6 |
LineNo. Expression
-1-: 358 ((otp_addr_sel == DigestAddrSel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T6 |
LineNo. Expression
-1-: 395 ((~init_done_o)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 420 ((digest_o != '0)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 186 case (state_q)
-2-: 191 if (init_req_i)
-3-: 193 if (1'b1)
-4-: 206 if (otp_gnt_i)
-5-: 215 if (otp_rvalid_i)
-6-: 217 if ((otp_err inside {NoError, MacroEccCorrError}))
-7-: 220 if ((otp_err != NoError))
-8-: 234 if (tlul_req_i)
-9-: 248 if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-: 251 if (otp_gnt_i)
-11-: 267 if (otp_rvalid_i)
-12-: 269 if ((otp_err inside {NoError, MacroEccCorrError}))
-13-: 272 if ((otp_err != NoError))
-14-: 288 if ((error_q == NoError))
-15-: 293 if (pending_tlul_error_q)
-16-: 296 if (tlul_req_i)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | Status | Tests |
ResetSt |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
ResetSt |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
ResetSt |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitSt |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T73,T47,T182 |
InitWaitSt |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T6,T127,T225 |
InitWaitSt |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IdleSt |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T6 |
IdleSt |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
ReadSt |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T6 |
ReadSt |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T14,T139,T141 |
ReadSt |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T4,T9,T116 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
Covered |
T110,T67,T174 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
Covered |
T2,T3,T6 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
Covered |
T174,T175,T223 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T2,T3,T6 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T19,T20,T21 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T2,T7,T6 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T7,T5,T8 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
Covered |
T7,T5,T8 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
Covered |
T2,T7,T6 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T19,T20,T21 |
LineNo. Expression
-1-: 314 if (ecc_err)
-2-: 316 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T82 |
1 |
0 |
Covered |
T82 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 321 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-: 324 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T2,T7,T5 |
1 |
0 |
Covered |
T2,T7,T6 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 461 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 464 if ((!rst_ni))
-2-: 471 if (tlul_gnt_o)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T3,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf
Assertion Details
AccessKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
DigestKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
DigestOffsetMustBeRepresentable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1142 |
1142 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
EccErrorState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
2866 |
0 |
0 |
T82 |
11994 |
2866 |
0 |
0 |
T145 |
543811 |
0 |
0 |
0 |
T166 |
108410 |
0 |
0 |
0 |
T226 |
35837 |
0 |
0 |
0 |
T227 |
62905 |
0 |
0 |
0 |
T228 |
8507 |
0 |
0 |
0 |
T229 |
11740 |
0 |
0 |
0 |
T230 |
73592 |
0 |
0 |
0 |
T231 |
165966 |
0 |
0 |
0 |
T232 |
57540 |
0 |
0 |
0 |
ErrorKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
FsmStateKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
InitDoneKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
InitReadLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
84313680 |
0 |
0 |
T1 |
18171 |
1023 |
0 |
0 |
T2 |
10983 |
5005 |
0 |
0 |
T3 |
12005 |
413 |
0 |
0 |
T4 |
66620 |
1308 |
0 |
0 |
T5 |
25260 |
19110 |
0 |
0 |
T6 |
10913 |
4509 |
0 |
0 |
T7 |
27700 |
22019 |
0 |
0 |
T11 |
12540 |
4531 |
0 |
0 |
T12 |
8654 |
3965 |
0 |
0 |
T13 |
15802 |
531 |
0 |
0 |
InitWriteLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
84313680 |
0 |
0 |
T1 |
18171 |
1023 |
0 |
0 |
T2 |
10983 |
5005 |
0 |
0 |
T3 |
12005 |
413 |
0 |
0 |
T4 |
66620 |
1308 |
0 |
0 |
T5 |
25260 |
19110 |
0 |
0 |
T6 |
10913 |
4509 |
0 |
0 |
T7 |
27700 |
22019 |
0 |
0 |
T11 |
12540 |
4531 |
0 |
0 |
T12 |
8654 |
3965 |
0 |
0 |
T13 |
15802 |
531 |
0 |
0 |
OffsetMustBeBlockAligned_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1142 |
1142 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
OtpAddrKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
OtpCmdKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
OtpErrorState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
36 |
0 |
0 |
T4 |
66620 |
0 |
0 |
0 |
T5 |
25260 |
0 |
0 |
0 |
T6 |
10913 |
1 |
0 |
0 |
T8 |
78898 |
0 |
0 |
0 |
T9 |
552962 |
0 |
0 |
0 |
T11 |
12540 |
0 |
0 |
0 |
T12 |
8654 |
0 |
0 |
0 |
T13 |
15802 |
0 |
0 |
0 |
T28 |
9738 |
0 |
0 |
0 |
T115 |
11847 |
0 |
0 |
0 |
T127 |
0 |
1 |
0 |
0 |
T174 |
0 |
1 |
0 |
0 |
T175 |
0 |
1 |
0 |
0 |
T223 |
0 |
2 |
0 |
0 |
T225 |
0 |
1 |
0 |
0 |
T233 |
0 |
1 |
0 |
0 |
T234 |
0 |
1 |
0 |
0 |
T235 |
0 |
1 |
0 |
0 |
T236 |
0 |
1 |
0 |
0 |
OtpReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
OtpSizeKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
OtpWdataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
ReadLockPropagation_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
169530280 |
0 |
0 |
T4 |
66620 |
3009 |
0 |
0 |
T5 |
25260 |
0 |
0 |
0 |
T8 |
78898 |
0 |
0 |
0 |
T9 |
552962 |
100275 |
0 |
0 |
T10 |
0 |
499303 |
0 |
0 |
T11 |
12540 |
0 |
0 |
0 |
T12 |
8654 |
0 |
0 |
0 |
T13 |
15802 |
1188 |
0 |
0 |
T14 |
0 |
854474 |
0 |
0 |
T26 |
0 |
1251 |
0 |
0 |
T28 |
9738 |
0 |
0 |
0 |
T46 |
0 |
4591 |
0 |
0 |
T71 |
0 |
907 |
0 |
0 |
T115 |
11847 |
0 |
0 |
0 |
T116 |
80278 |
72362 |
0 |
0 |
T177 |
0 |
21151 |
0 |
0 |
SizeMustBeBlockAligned_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1142 |
1142 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
TlulGntKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
TlulRdataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
TlulReadOnReadLock_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
7965 |
0 |
0 |
T4 |
66620 |
1 |
0 |
0 |
T5 |
25260 |
4 |
0 |
0 |
T6 |
10913 |
0 |
0 |
0 |
T7 |
27700 |
6 |
0 |
0 |
T8 |
78898 |
10 |
0 |
0 |
T9 |
0 |
50 |
0 |
0 |
T10 |
0 |
31 |
0 |
0 |
T11 |
12540 |
0 |
0 |
0 |
T12 |
8654 |
0 |
0 |
0 |
T13 |
15802 |
0 |
0 |
0 |
T14 |
0 |
35 |
0 |
0 |
T26 |
0 |
1 |
0 |
0 |
T28 |
9738 |
0 |
0 |
0 |
T115 |
11847 |
0 |
0 |
0 |
T116 |
0 |
20 |
0 |
0 |
T177 |
0 |
16 |
0 |
0 |
TlulRerrorKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
TlulRvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
WriteLockPropagation_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
2362495 |
0 |
0 |
T27 |
724755 |
35019 |
0 |
0 |
T50 |
169082 |
40372 |
0 |
0 |
T64 |
0 |
4101 |
0 |
0 |
T67 |
0 |
22148 |
0 |
0 |
T73 |
14581 |
0 |
0 |
0 |
T76 |
0 |
72887 |
0 |
0 |
T85 |
14843 |
0 |
0 |
0 |
T87 |
0 |
8977 |
0 |
0 |
T108 |
59798 |
0 |
0 |
0 |
T111 |
0 |
10079 |
0 |
0 |
T113 |
0 |
25982 |
0 |
0 |
T114 |
0 |
7571 |
0 |
0 |
T118 |
25153 |
0 |
0 |
0 |
T119 |
33621 |
0 |
0 |
0 |
T126 |
0 |
14565 |
0 |
0 |
T127 |
13188 |
0 |
0 |
0 |
T128 |
33931 |
0 |
0 |
0 |
T129 |
10586 |
0 |
0 |
0 |
gen_digest_write_lock.DigestWriteLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
27965507 |
0 |
0 |
T4 |
66620 |
55210 |
0 |
0 |
T5 |
25260 |
2904 |
0 |
0 |
T6 |
10913 |
3403 |
0 |
0 |
T8 |
78898 |
0 |
0 |
0 |
T9 |
552962 |
0 |
0 |
0 |
T11 |
12540 |
0 |
0 |
0 |
T12 |
8654 |
0 |
0 |
0 |
T13 |
15802 |
0 |
0 |
0 |
T26 |
0 |
3364 |
0 |
0 |
T27 |
0 |
508836 |
0 |
0 |
T28 |
9738 |
0 |
0 |
0 |
T40 |
0 |
33953 |
0 |
0 |
T46 |
0 |
3127 |
0 |
0 |
T50 |
0 |
144010 |
0 |
0 |
T115 |
11847 |
0 |
0 |
0 |
T116 |
0 |
3572 |
0 |
0 |
T118 |
0 |
2637 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf
| Line No. | Total | Covered | Percent |
TOTAL | | 91 | 91 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
ALWAYS | 164 | 68 | 68 | 100.00 |
CONT_ASSIGN | 334 | 1 | 1 | 100.00 |
CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 342 | 1 | 1 | 100.00 |
CONT_ASSIGN | 349 | 1 | 1 | 100.00 |
CONT_ASSIGN | 350 | 1 | 1 | 100.00 |
CONT_ASSIGN | 354 | 1 | 1 | 100.00 |
CONT_ASSIGN | 358 | 1 | 1 | 100.00 |
CONT_ASSIGN | 395 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 454 | 1 | 1 | 100.00 |
ALWAYS | 461 | 3 | 3 | 100.00 |
ALWAYS | 464 | 8 | 8 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
138 |
1 |
1 |
149 |
1 |
1 |
164 |
1 |
1 |
167 |
1 |
1 |
170 |
1 |
1 |
171 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
179 |
1 |
1 |
182 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
186 |
1 |
1 |
191 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
196 |
|
unreachable |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
207 |
1 |
1 |
|
|
|
MISSING_ELSE |
215 |
1 |
1 |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
220 |
1 |
1 |
221 |
1 |
1 |
|
|
|
MISSING_ELSE |
224 |
1 |
1 |
225 |
1 |
1 |
|
|
|
MISSING_ELSE |
233 |
1 |
1 |
234 |
1 |
1 |
235 |
1 |
1 |
236 |
1 |
1 |
237 |
1 |
1 |
|
|
|
MISSING_ELSE |
246 |
1 |
1 |
248 |
1 |
1 |
249 |
1 |
1 |
250 |
1 |
1 |
251 |
1 |
1 |
252 |
1 |
1 |
|
|
|
MISSING_ELSE |
255 |
1 |
1 |
256 |
1 |
1 |
257 |
1 |
1 |
258 |
1 |
1 |
266 |
1 |
1 |
267 |
1 |
1 |
268 |
1 |
1 |
269 |
1 |
1 |
270 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
|
|
|
MISSING_ELSE |
276 |
1 |
1 |
277 |
1 |
1 |
279 |
1 |
1 |
|
|
|
MISSING_ELSE |
288 |
1 |
1 |
289 |
1 |
1 |
|
|
|
MISSING_ELSE |
293 |
1 |
1 |
294 |
1 |
1 |
295 |
1 |
1 |
296 |
1 |
1 |
297 |
1 |
1 |
298 |
1 |
1 |
|
|
|
MISSING_ELSE |
314 |
1 |
1 |
315 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
321 |
1 |
1 |
322 |
1 |
1 |
323 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
334 |
1 |
1 |
336 |
1 |
1 |
342 |
1 |
1 |
349 |
1 |
1 |
350 |
1 |
1 |
354 |
1 |
1 |
358 |
1 |
1 |
395 |
1 |
1 |
420 |
1 |
1 |
454 |
1 |
1 |
461 |
3 |
3 |
464 |
1 |
1 |
465 |
1 |
1 |
466 |
1 |
1 |
467 |
1 |
1 |
469 |
1 |
1 |
470 |
1 |
1 |
471 |
1 |
1 |
472 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf
| Total | Covered | Percent |
Conditions | 33 | 33 | 100.00 |
Logical | 33 | 33 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 220
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T11,T72,T86 |
LINE 272
EXPRESSION (otp_err != NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T6,T4 |
1 | Covered | T26,T174,T76 |
LINE 288
EXPRESSION (error_q == NoError)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T7,T6 |
1 | Covered | T19,T20,T21 |
LINE 316
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T82 |
1 | Covered | T82 |
LINE 324
EXPRESSION (state_q != ErrorSt)
----------1---------
-1- | Status | Tests |
0 | Covered | T2,T7,T6 |
1 | Covered | T2,T7,T6 |
LINE 336
EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T6,T4 |
LINE 336
SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
------1------ ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T7,T5,T13 |
1 | 1 | Covered | T2,T6,T4 |
LINE 336
SUB-EXPRESSION (tlul_rerror_o == '0)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 342
EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
--------------------1------------------- ------------------2------------------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T2,T7,T6 |
LINE 349
EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
---------------1---------------
-1- | Status | Tests |
0 | Covered | T2,T6,T4 |
1 | Covered | T1,T2,T3 |
LINE 349
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 358
EXPRESSION
Number Term
1 (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))
-1- | Status | Tests |
0 | Covered | T2,T6,T4 |
1 | Covered | T1,T2,T3 |
LINE 358
SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 395
EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 420
EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T116,T46 |
LINE 420
SUB-EXPRESSION (digest_o != '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T116,T46 |
FSM Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
7 |
7 |
100.00 |
(Not included in score) |
Transitions |
13 |
12 |
92.31 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
ErrorSt |
224 |
Covered |
T2,T7,T6 |
IdleSt |
196 |
Covered |
T1,T2,T3 |
InitSt |
194 |
Covered |
T1,T2,T3 |
InitWaitSt |
207 |
Covered |
T1,T2,T3 |
ReadSt |
236 |
Covered |
T2,T6,T4 |
ReadWaitSt |
252 |
Covered |
T2,T6,T4 |
ResetSt |
190 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests | Exclude Annotation |
IdleSt->ErrorSt |
315 |
Covered |
T7,T5,T11 |
|
IdleSt->ReadSt |
236 |
Covered |
T2,T6,T4 |
|
InitSt->ErrorSt |
315 |
Covered |
T2,T12,T115 |
|
InitSt->InitWaitSt |
207 |
Covered |
T1,T2,T3 |
|
InitWaitSt->ErrorSt |
224 |
Covered |
T6,T73,T127 |
|
InitWaitSt->IdleSt |
218 |
Covered |
T1,T2,T3 |
|
ReadSt->ErrorSt |
315 |
Not Covered |
|
|
ReadSt->IdleSt |
255 |
Covered |
T13,T9,T116 |
|
ReadSt->ReadWaitSt |
252 |
Covered |
T2,T6,T4 |
|
ReadWaitSt->ErrorSt |
276 |
Covered |
T185,T102,T221 |
|
ReadWaitSt->IdleSt |
270 |
Covered |
T2,T6,T4 |
|
ResetSt->ErrorSt |
315 |
Covered |
T80,T81,T82 |
|
ResetSt->IdleSt |
196 |
Excluded |
|
VC_COV_UNR |
ResetSt->InitSt |
194 |
Covered |
T1,T2,T3 |
|
Summary for FSM :: error_q
| Total | Covered | Percent | |
States |
5 |
5 |
100.00 |
(Not included in score) |
Transitions |
11 |
10 |
90.91 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: error_q
states | Line No. | Covered | Tests |
AccessError |
256 |
Covered |
T13,T9,T116 |
CheckFailError |
317 |
Covered |
T82 |
FsmStateError |
289 |
Covered |
T2,T7,T6 |
MacroEccCorrError |
221 |
Covered |
T11,T26,T72 |
NoError |
235 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests | Exclude Annotation |
AccessError->CheckFailError |
317 |
Excluded |
|
VC_COV_UNR |
AccessError->FsmStateError |
325 |
Covered |
T9,T116,T173 |
|
AccessError->MacroEccCorrError |
221 |
Excluded |
|
VC_COV_UNR |
AccessError->NoError |
235 |
Covered |
T13,T9,T10 |
|
CheckFailError->AccessError |
256 |
Excluded |
|
VC_COV_UNR |
CheckFailError->FsmStateError |
325 |
Excluded |
|
VC_COV_UNR |
CheckFailError->MacroEccCorrError |
221 |
Excluded |
|
VC_COV_UNR |
CheckFailError->NoError |
235 |
Covered |
T82 |
|
FsmStateError->AccessError |
256 |
Excluded |
|
VC_COV_UNR |
FsmStateError->CheckFailError |
317 |
Excluded |
|
VC_COV_UNR |
FsmStateError->MacroEccCorrError |
221 |
Excluded |
|
VC_COV_UNR |
FsmStateError->NoError |
235 |
Covered |
T2,T7,T6 |
|
MacroEccCorrError->AccessError |
256 |
Excluded |
|
VC_COV_UNR |
MacroEccCorrError->CheckFailError |
317 |
Not Covered |
|
|
MacroEccCorrError->FsmStateError |
325 |
Covered |
T11,T72,T86 |
|
MacroEccCorrError->NoError |
235 |
Covered |
T26,T76,T87 |
|
NoError->AccessError |
256 |
Covered |
T13,T9,T116 |
|
NoError->CheckFailError |
317 |
Covered |
T82 |
|
NoError->FsmStateError |
289 |
Covered |
T2,T7,T6 |
|
NoError->MacroEccCorrError |
221 |
Covered |
T11,T26,T72 |
|
Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf
| Line No. | Total | Covered | Percent |
Branches |
|
44 |
44 |
100.00 |
TERNARY |
336 |
2 |
2 |
100.00 |
TERNARY |
349 |
2 |
2 |
100.00 |
TERNARY |
358 |
2 |
2 |
100.00 |
TERNARY |
395 |
2 |
2 |
100.00 |
TERNARY |
420 |
2 |
2 |
100.00 |
CASE |
186 |
23 |
23 |
100.00 |
IF |
314 |
3 |
3 |
100.00 |
IF |
321 |
3 |
3 |
100.00 |
IF |
461 |
2 |
2 |
100.00 |
IF |
464 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 336 ((tlul_rvalid_o && (tlul_rerror_o == '0))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T6,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 349 ((otp_addr_sel == DigestAddrSel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T6,T4 |
LineNo. Expression
-1-: 358 ((otp_addr_sel == DigestAddrSel)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T6,T4 |
LineNo. Expression
-1-: 395 ((~init_done_o)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 420 ((digest_o != '0)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T116,T46 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 186 case (state_q)
-2-: 191 if (init_req_i)
-3-: 193 if (1'b1)
-4-: 206 if (otp_gnt_i)
-5-: 215 if (otp_rvalid_i)
-6-: 217 if ((otp_err inside {NoError, MacroEccCorrError}))
-7-: 220 if ((otp_err != NoError))
-8-: 234 if (tlul_req_i)
-9-: 248 if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-: 251 if (otp_gnt_i)
-11-: 267 if (otp_rvalid_i)
-12-: 269 if ((otp_err inside {NoError, MacroEccCorrError}))
-13-: 272 if ((otp_err != NoError))
-14-: 288 if ((error_q == NoError))
-15-: 293 if (pending_tlul_error_q)
-16-: 296 if (tlul_req_i)
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | -16- | Status | Tests |
ResetSt |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
ResetSt |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Unreachable |
|
ResetSt |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitSt |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitSt |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T11,T72,T86 |
InitWaitSt |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
InitWaitSt |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T73,T182,T237 |
InitWaitSt |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
IdleSt |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T2,T6,T4 |
IdleSt |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
ReadSt |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T6,T4 |
ReadSt |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T139,T141,T106 |
ReadSt |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
- |
- |
Covered |
T13,T9,T116 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
1 |
- |
- |
- |
Covered |
T26,T174,T76 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
1 |
0 |
- |
- |
- |
Covered |
T2,T6,T4 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
0 |
- |
- |
- |
- |
Covered |
T185,T102,T221 |
ReadWaitSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
- |
- |
- |
Covered |
T2,T6,T4 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T19,T20,T21 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
- |
- |
Covered |
T2,T7,T6 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
1 |
- |
Covered |
T7,T5,T8 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
1 |
Covered |
T7,T5,T8 |
ErrorSt |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
0 |
0 |
Covered |
T2,T7,T6 |
default |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
- |
Covered |
T19,T20,T21 |
LineNo. Expression
-1-: 314 if (ecc_err)
-2-: 316 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T82 |
1 |
0 |
Covered |
T82 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 321 if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-: 324 if ((state_q != ErrorSt))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T2,T7,T6 |
1 |
0 |
Covered |
T2,T7,T6 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 461 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 464 if ((!rst_ni))
-2-: 471 if (tlul_gnt_o)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T7,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf
Assertion Details
AccessKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
DigestKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
DigestOffsetMustBeRepresentable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1142 |
1142 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
EccErrorState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
2866 |
0 |
0 |
T82 |
11994 |
2866 |
0 |
0 |
T145 |
543811 |
0 |
0 |
0 |
T166 |
108410 |
0 |
0 |
0 |
T226 |
35837 |
0 |
0 |
0 |
T227 |
62905 |
0 |
0 |
0 |
T228 |
8507 |
0 |
0 |
0 |
T229 |
11740 |
0 |
0 |
0 |
T230 |
73592 |
0 |
0 |
0 |
T231 |
165966 |
0 |
0 |
0 |
T232 |
57540 |
0 |
0 |
0 |
ErrorKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
FsmStateKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
InitDoneKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
InitReadLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
84491684 |
0 |
0 |
T1 |
18171 |
1040 |
0 |
0 |
T2 |
10983 |
5022 |
0 |
0 |
T3 |
12005 |
447 |
0 |
0 |
T4 |
66620 |
1495 |
0 |
0 |
T5 |
25260 |
19144 |
0 |
0 |
T6 |
10913 |
4526 |
0 |
0 |
T7 |
27700 |
22087 |
0 |
0 |
T11 |
12540 |
4582 |
0 |
0 |
T12 |
8654 |
3982 |
0 |
0 |
T13 |
15802 |
599 |
0 |
0 |
InitWriteLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
84491684 |
0 |
0 |
T1 |
18171 |
1040 |
0 |
0 |
T2 |
10983 |
5022 |
0 |
0 |
T3 |
12005 |
447 |
0 |
0 |
T4 |
66620 |
1495 |
0 |
0 |
T5 |
25260 |
19144 |
0 |
0 |
T6 |
10913 |
4526 |
0 |
0 |
T7 |
27700 |
22087 |
0 |
0 |
T11 |
12540 |
4582 |
0 |
0 |
T12 |
8654 |
3982 |
0 |
0 |
T13 |
15802 |
599 |
0 |
0 |
OffsetMustBeBlockAligned_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1142 |
1142 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
OtpAddrKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
OtpCmdKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
OtpErrorState_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
38 |
0 |
0 |
T25 |
264687 |
0 |
0 |
0 |
T49 |
284273 |
0 |
0 |
0 |
T73 |
14581 |
1 |
0 |
0 |
T85 |
14843 |
0 |
0 |
0 |
T102 |
0 |
1 |
0 |
0 |
T108 |
59798 |
0 |
0 |
0 |
T119 |
33621 |
0 |
0 |
0 |
T127 |
13188 |
0 |
0 |
0 |
T128 |
33931 |
0 |
0 |
0 |
T129 |
10586 |
0 |
0 |
0 |
T182 |
0 |
1 |
0 |
0 |
T185 |
0 |
1 |
0 |
0 |
T221 |
0 |
2 |
0 |
0 |
T237 |
0 |
1 |
0 |
0 |
T238 |
0 |
1 |
0 |
0 |
T239 |
0 |
1 |
0 |
0 |
T240 |
0 |
1 |
0 |
0 |
T241 |
0 |
1 |
0 |
0 |
T242 |
5782 |
0 |
0 |
0 |
OtpReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
OtpSizeKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
OtpWdataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
ReadLockPropagation_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
169623571 |
0 |
0 |
T4 |
66620 |
1218 |
0 |
0 |
T5 |
25260 |
0 |
0 |
0 |
T8 |
78898 |
0 |
0 |
0 |
T9 |
552962 |
362668 |
0 |
0 |
T10 |
0 |
217753 |
0 |
0 |
T11 |
12540 |
0 |
0 |
0 |
T12 |
8654 |
0 |
0 |
0 |
T13 |
15802 |
1186 |
0 |
0 |
T14 |
0 |
857816 |
0 |
0 |
T26 |
0 |
1249 |
0 |
0 |
T28 |
9738 |
0 |
0 |
0 |
T46 |
0 |
3640 |
0 |
0 |
T71 |
0 |
905 |
0 |
0 |
T115 |
11847 |
0 |
0 |
0 |
T116 |
80278 |
72352 |
0 |
0 |
T177 |
0 |
21149 |
0 |
0 |
SizeMustBeBlockAligned_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1142 |
1142 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
TlulGntKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
TlulRdataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
TlulReadOnReadLock_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
7772 |
0 |
0 |
T4 |
66620 |
0 |
0 |
0 |
T5 |
25260 |
5 |
0 |
0 |
T6 |
10913 |
0 |
0 |
0 |
T7 |
27700 |
8 |
0 |
0 |
T8 |
78898 |
15 |
0 |
0 |
T9 |
0 |
41 |
0 |
0 |
T10 |
0 |
34 |
0 |
0 |
T11 |
12540 |
0 |
0 |
0 |
T12 |
8654 |
0 |
0 |
0 |
T13 |
15802 |
2 |
0 |
0 |
T14 |
0 |
31 |
0 |
0 |
T26 |
0 |
1 |
0 |
0 |
T28 |
9738 |
0 |
0 |
0 |
T46 |
0 |
1 |
0 |
0 |
T115 |
11847 |
0 |
0 |
0 |
T116 |
0 |
18 |
0 |
0 |
TlulRerrorKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
TlulRvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |
WriteLockPropagation_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
1486300 |
0 |
0 |
T27 |
724755 |
27990 |
0 |
0 |
T50 |
169082 |
54055 |
0 |
0 |
T51 |
0 |
233724 |
0 |
0 |
T73 |
14581 |
0 |
0 |
0 |
T85 |
14843 |
0 |
0 |
0 |
T87 |
0 |
15936 |
0 |
0 |
T108 |
59798 |
0 |
0 |
0 |
T118 |
25153 |
0 |
0 |
0 |
T119 |
33621 |
0 |
0 |
0 |
T127 |
13188 |
0 |
0 |
0 |
T128 |
33931 |
0 |
0 |
0 |
T129 |
10586 |
0 |
0 |
0 |
T139 |
0 |
8014 |
0 |
0 |
T141 |
0 |
5276 |
0 |
0 |
T221 |
0 |
14549 |
0 |
0 |
T243 |
0 |
4677 |
0 |
0 |
T244 |
0 |
9581 |
0 |
0 |
T245 |
0 |
15400 |
0 |
0 |
gen_digest_write_lock.DigestWriteLocksPartition_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
13668745 |
0 |
0 |
T5 |
25260 |
2887 |
0 |
0 |
T8 |
78898 |
0 |
0 |
0 |
T9 |
552962 |
0 |
0 |
0 |
T11 |
12540 |
0 |
0 |
0 |
T12 |
8654 |
0 |
0 |
0 |
T13 |
15802 |
0 |
0 |
0 |
T26 |
48213 |
0 |
0 |
0 |
T27 |
0 |
395085 |
0 |
0 |
T28 |
9738 |
0 |
0 |
0 |
T40 |
0 |
49202 |
0 |
0 |
T46 |
0 |
3110 |
0 |
0 |
T50 |
0 |
143789 |
0 |
0 |
T73 |
0 |
2805 |
0 |
0 |
T108 |
0 |
45067 |
0 |
0 |
T115 |
11847 |
0 |
0 |
0 |
T116 |
80278 |
3538 |
0 |
0 |
T162 |
0 |
2414 |
0 |
0 |
T218 |
0 |
3839 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
418887820 |
418028873 |
0 |
0 |
T1 |
18171 |
18106 |
0 |
0 |
T2 |
10983 |
10735 |
0 |
0 |
T3 |
12005 |
11725 |
0 |
0 |
T4 |
66620 |
65527 |
0 |
0 |
T5 |
25260 |
25007 |
0 |
0 |
T6 |
10913 |
10643 |
0 |
0 |
T7 |
27700 |
27398 |
0 |
0 |
T11 |
12540 |
12258 |
0 |
0 |
T12 |
8654 |
8433 |
0 |
0 |
T13 |
15802 |
15530 |
0 |
0 |