Module Definition
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Module : tlul_err_resp
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_tlul_lc_gate.u_tlul_err_resp 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate.u_tlul_err_resp

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.66 98.04 88.89 85.71 95.65 50.00 u_tlul_lc_gate


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_intg_gen 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_err_resp
Line No.TotalCoveredPercent
TOTAL2121100.00
ALWAYS341414100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
36 1 1
37 1 1
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
MISSING_ELSE
51 1 1
52 1 1
53 1 1
55 1 1
58 1 1
59 1 1
65 1 1


Cond Coverage for Module : tlul_err_resp
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       40
 EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
             -------1-------    -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T5,T116
11CoveredT3,T7,T4

 LINE       42
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT38,T17,T18
11CoveredT3,T7,T4

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------
-1-StatusTests
0CoveredT3,T7,T4
1CoveredT1,T2,T3

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : tlul_err_resp
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 59 2 2 100.00
IF 34 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 59 ((err_opcode == Get)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T7,T4


LineNo. Expression -1-: 34 if ((!rst_ni)) -2-: 40 if ((err_rsp_pending && tl_h_i.d_ready)) -3-: 42 if ((tl_h_i.a_valid && tl_h_o_int.a_ready))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T3,T7,T4
0 0 1 Covered T3,T7,T4
0 0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%