Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7390506	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

7499258

1

T1

267

T2

996

T3

247

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	8444111	1			T1	943		T2	3390		T3	977
values[0x0]	2442528	1			T1	151		T2	148		T3	127
values[0x1]	4003125	1			T1	159		T2	156		T3	155

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4753965	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

10135799

1

T1

558

T2

1755

T3

529

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56768	1			T1	13		T2	17		T11	11
valid_sources[0x01]	59569	1			T1	6		T2	14		T3	9
valid_sources[0x02]	50757	1			T2	13		T3	2		T11	25
valid_sources[0x03]	109583	1			T1	20		T2	17		T3	3
valid_sources[0x04]	56435	1			T1	20		T2	20		T3	3
valid_sources[0x05]	53005	1			T1	3		T2	14		T3	1
valid_sources[0x06]	53073	1			T1	14		T2	17		T3	6
valid_sources[0x07]	50920	1			T1	3		T2	10		T3	10
valid_sources[0x08]	52176	1			T1	4		T2	18		T3	5
valid_sources[0x09]	61278	1			T1	6		T2	13		T3	3
valid_sources[0x0a]	50036	1			T1	6		T2	14		T3	8
valid_sources[0x0b]	52844	1			T1	3		T2	14		T3	4
valid_sources[0x0c]	52180	1			T1	7		T2	6		T3	6
valid_sources[0x0d]	96322	1			T1	3		T2	18		T3	4
valid_sources[0x0e]	50564	1			T2	11		T3	1		T5	2
valid_sources[0x0f]	67066	1			T1	6		T2	15		T3	3
valid_sources[0x10]	52054	1			T2	20		T3	2		T11	1
valid_sources[0x11]	55558	1			T1	3		T2	14		T3	6
valid_sources[0x12]	52431	1			T1	4		T2	14		T3	3
valid_sources[0x13]	51525	1			T1	16		T2	21		T3	1
valid_sources[0x14]	53652	1			T1	2		T2	17		T3	19
valid_sources[0x15]	52155	1			T1	4		T2	21		T3	3
valid_sources[0x16]	55316	1			T1	3		T2	9		T3	10
valid_sources[0x17]	51370	1			T2	12		T3	10		T5	10
valid_sources[0x18]	57468	1			T2	12		T3	12		T5	1
valid_sources[0x19]	53625	1			T2	20		T3	4		T11	23
valid_sources[0x1a]	51736	1			T1	7		T2	11		T3	6
valid_sources[0x1b]	50659	1			T2	19		T3	4		T5	7
valid_sources[0x1c]	106134	1			T2	16		T3	10		T5	3
valid_sources[0x1d]	52266	1			T1	3		T2	18		T3	13
valid_sources[0x1e]	55105	1			T1	2		T2	16		T3	4
valid_sources[0x1f]	51995	1			T1	4		T2	13		T5	2
valid_sources[0x20]	62828	1			T1	7		T2	5		T3	5
valid_sources[0x21]	69139	1			T2	11		T3	4		T5	2
valid_sources[0x22]	51241	1			T1	9		T2	12		T3	11
valid_sources[0x23]	51767	1			T1	6		T2	20		T3	3
valid_sources[0x24]	62184	1			T1	13		T2	18		T3	4
valid_sources[0x25]	79325	1			T2	8		T3	3		T5	3
valid_sources[0x26]	61424	1			T1	5		T2	21		T3	15
valid_sources[0x27]	52965	1			T2	14		T3	3		T5	2
valid_sources[0x28]	56822	1			T1	5		T2	11		T3	3
valid_sources[0x29]	59667	1			T2	19		T3	2		T11	50
valid_sources[0x2a]	52181	1			T2	10		T3	2		T5	1
valid_sources[0x2b]	123712	1			T1	5		T2	18		T3	3
valid_sources[0x2c]	61730	1			T1	2		T2	15		T3	9
valid_sources[0x2d]	68876	1			T1	4		T2	11		T3	8
valid_sources[0x2e]	51807	1			T1	5		T2	6		T3	3
valid_sources[0x2f]	55084	1			T1	4		T2	8		T3	6
valid_sources[0x30]	51139	1			T1	18		T2	16		T3	4
valid_sources[0x31]	67737	1			T1	1		T2	18		T3	6
valid_sources[0x32]	50829	1			T2	8		T3	8		T5	14
valid_sources[0x33]	51971	1			T1	6		T2	10		T3	6
valid_sources[0x34]	52695	1			T1	7		T2	6		T3	18
valid_sources[0x35]	55731	1			T1	2		T2	14		T3	3
valid_sources[0x36]	52067	1			T1	3		T2	12		T3	1
valid_sources[0x37]	61958	1			T1	2		T2	11		T3	2
valid_sources[0x38]	50883	1			T1	4		T2	11		T3	13
valid_sources[0x39]	52299	1			T1	5		T2	18		T3	9
valid_sources[0x3a]	70052	1			T2	17		T3	2		T5	5
valid_sources[0x3b]	50722	1			T1	2		T2	9		T3	3
valid_sources[0x3c]	53657	1			T1	3		T2	15		T3	9
valid_sources[0x3d]	53648	1			T1	8		T2	11		T3	5
valid_sources[0x3e]	55582	1			T1	7		T2	11		T3	15
valid_sources[0x3f]	51956	1			T1	6		T2	11		T3	4
valid_sources[0x40]	53140	1			T1	7		T2	12		T3	1
valid_sources[0x41]	52596	1			T1	3		T2	11		T11	6
valid_sources[0x42]	51845	1			T2	10		T3	4		T5	4
valid_sources[0x43]	53367	1			T1	13		T2	10		T3	3
valid_sources[0x44]	52898	1			T1	5		T2	11		T3	4
valid_sources[0x45]	52243	1			T2	24		T3	9		T5	1
valid_sources[0x46]	51679	1			T1	17		T2	11		T3	2
valid_sources[0x47]	52082	1			T1	4		T2	12		T3	13
valid_sources[0x48]	61028	1			T1	6		T2	17		T3	2
valid_sources[0x49]	51570	1			T1	2		T2	12		T3	8
valid_sources[0x4a]	55006	1			T1	24		T2	20		T5	2
valid_sources[0x4b]	60578	1			T1	6		T2	13		T3	3
valid_sources[0x4c]	52810	1			T1	2		T2	14		T5	1
valid_sources[0x4d]	52855	1			T1	6		T2	15		T3	15
valid_sources[0x4e]	148518	1			T2	14		T3	2		T5	3
valid_sources[0x4f]	51653	1			T1	17		T2	13		T3	6
valid_sources[0x50]	53478	1			T1	8		T2	18		T3	3
valid_sources[0x51]	51911	1			T1	10		T2	22		T3	4
valid_sources[0x52]	50737	1			T1	5		T2	13		T5	8
valid_sources[0x53]	54385	1			T1	1		T2	16		T3	7
valid_sources[0x54]	52242	1			T1	7		T2	16		T3	11
valid_sources[0x55]	60645	1			T1	2		T2	19		T106	30
valid_sources[0x56]	51586	1			T2	11		T3	1		T5	2
valid_sources[0x57]	72067	1			T1	4		T2	22		T5	9
valid_sources[0x58]	56277	1			T2	19		T3	7		T5	3
valid_sources[0x59]	51191	1			T2	12		T3	2		T5	2
valid_sources[0x5a]	52951	1			T1	10		T2	8		T11	36
valid_sources[0x5b]	54493	1			T1	1		T2	18		T3	3
valid_sources[0x5c]	55071	1			T1	4		T2	15		T3	5
valid_sources[0x5d]	54209	1			T1	5		T2	15		T3	5
valid_sources[0x5e]	52638	1			T2	13		T3	3		T5	5
valid_sources[0x5f]	64497	1			T1	5		T2	16		T3	4
valid_sources[0x60]	51381	1			T1	7		T2	13		T3	1
valid_sources[0x61]	55188	1			T1	15		T2	18		T3	5
valid_sources[0x62]	63474	1			T1	8		T2	6		T3	1
valid_sources[0x63]	59046	1			T1	12		T2	15		T11	6
valid_sources[0x64]	59742	1			T1	5		T2	9		T3	4
valid_sources[0x65]	52359	1			T1	1		T2	7		T3	1
valid_sources[0x66]	50623	1			T1	13		T2	20		T3	6
valid_sources[0x67]	51611	1			T1	2		T2	10		T3	2
valid_sources[0x68]	60649	1			T2	21		T3	9		T5	1
valid_sources[0x69]	131851	1			T1	8		T2	15		T3	1
valid_sources[0x6a]	49789	1			T1	14		T2	12		T3	3
valid_sources[0x6b]	59454	1			T2	21		T3	6		T5	2
valid_sources[0x6c]	60913	1			T1	2		T2	21		T3	7
valid_sources[0x6d]	51290	1			T1	2		T2	22		T3	6
valid_sources[0x6e]	55691	1			T1	19		T2	16		T3	2
valid_sources[0x6f]	51678	1			T1	1		T2	9		T3	1
valid_sources[0x70]	51959	1			T1	17		T2	20		T11	9
valid_sources[0x71]	58372	1			T2	14		T3	5		T5	4
valid_sources[0x72]	50572	1			T1	1		T2	11		T3	9
valid_sources[0x73]	52390	1			T2	16		T3	5		T5	4
valid_sources[0x74]	56924	1			T1	10		T2	21		T3	1
valid_sources[0x75]	52709	1			T1	7		T2	11		T3	14
valid_sources[0x76]	53144	1			T1	8		T2	13		T3	6
valid_sources[0x77]	51730	1			T1	8		T2	16		T3	1
valid_sources[0x78]	50750	1			T1	2		T2	14		T3	5
valid_sources[0x79]	49961	1			T1	2		T2	19		T3	6
valid_sources[0x7a]	49972	1			T1	1		T2	20		T3	5
valid_sources[0x7b]	53197	1			T2	19		T3	6		T5	12
valid_sources[0x7c]	50442	1			T1	9		T2	12		T3	3
valid_sources[0x7d]	53522	1			T1	1		T2	13		T3	5
valid_sources[0x7e]	53385	1			T1	1		T2	8		T3	3
valid_sources[0x7f]	53994	1			T1	10		T2	9		T3	16
valid_sources[0x80]	53789	1			T2	17		T3	9		T5	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3510246

1

T1

140

T2

862

T3

141

values[0x0]

all_enables

biggest_size

2033180

1

T1

75

T2

76

T3

48

values[0x1]

all_enables

biggest_size

1955832

1

T1

52

T2

58

T3

58

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	264109	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

9612431

1

T2

40

T10

40

T4

60

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2454780	1			T2	20		T10	20		T4	30
values[0x0]	3603079	1			T2	8		T10	9		T4	16
values[0x1]	3818681	1			T2	12		T10	11		T4	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	95535	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

9781005

1

T2

40

T10

40

T4

60

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	38647	1			T7	1		T108	3		T8	2
valid_sources[0x01]	40444	1			T6	1		T8	5		T96	4
valid_sources[0x02]	38975	1			T108	2		T8	4		T9	12
valid_sources[0x03]	38279	1			T8	7		T14	1045		T282	1
valid_sources[0x04]	38231	1			T2	3		T58	1		T8	4
valid_sources[0x05]	40047	1			T11	1		T8	5		T109	1
valid_sources[0x06]	39167	1			T106	1		T7	1		T8	6
valid_sources[0x07]	37385	1			T6	1		T11	1		T8	2
valid_sources[0x08]	38937	1			T11	1		T58	1		T8	8
valid_sources[0x09]	38162	1			T8	4		T109	2		T14	1015
valid_sources[0x0a]	39217	1			T10	1		T8	4		T9	6
valid_sources[0x0b]	38847	1			T6	1		T11	2		T8	6
valid_sources[0x0c]	39186	1			T2	1		T58	2		T8	5
valid_sources[0x0d]	38079	1			T4	4		T58	1		T8	5
valid_sources[0x0e]	37423	1			T106	3		T8	1		T65	2
valid_sources[0x0f]	39073	1			T11	1		T7	1		T58	1
valid_sources[0x10]	38092	1			T8	6		T94	2		T96	1
valid_sources[0x11]	38830	1			T10	1		T7	1		T8	1
valid_sources[0x12]	40046	1			T106	1		T8	5		T9	3
valid_sources[0x13]	38304	1			T8	6		T98	1		T9	10
valid_sources[0x14]	38628	1			T7	1		T8	7		T97	1
valid_sources[0x15]	37849	1			T8	5		T150	2		T110	1
valid_sources[0x16]	37850	1			T8	7		T14	1144		T191	1
valid_sources[0x17]	39416	1			T108	2		T58	1		T8	4
valid_sources[0x18]	37518	1			T2	3		T6	2		T8	6
valid_sources[0x19]	37489	1			T2	1		T106	3		T8	8
valid_sources[0x1a]	39186	1			T11	4		T106	3		T7	1
valid_sources[0x1b]	38812	1			T2	1		T6	1		T8	3
valid_sources[0x1c]	37107	1			T8	2		T65	1		T9	2
valid_sources[0x1d]	38836	1			T10	1		T58	1		T8	4
valid_sources[0x1e]	37690	1			T10	2		T58	1		T8	7
valid_sources[0x1f]	39742	1			T106	6		T58	1		T8	6
valid_sources[0x20]	39282	1			T8	4		T9	23		T109	3
valid_sources[0x21]	38497	1			T106	1		T8	6		T9	17
valid_sources[0x22]	37287	1			T106	2		T8	7		T256	1
valid_sources[0x23]	38347	1			T6	1		T7	1		T58	3
valid_sources[0x24]	39292	1			T4	1		T8	10		T338	1
valid_sources[0x25]	38559	1			T58	1		T8	4		T97	2
valid_sources[0x26]	38705	1			T58	1		T8	3		T98	2
valid_sources[0x27]	37653	1			T2	1		T4	1		T11	2
valid_sources[0x28]	37676	1			T8	5		T110	3		T14	1003
valid_sources[0x29]	38952	1			T6	1		T13	13		T8	7
valid_sources[0x2a]	39560	1			T10	1		T6	2		T8	3
valid_sources[0x2b]	38148	1			T106	6		T58	1		T8	6
valid_sources[0x2c]	37756	1			T58	2		T8	1		T9	1
valid_sources[0x2d]	39485	1			T11	2		T58	1		T8	3
valid_sources[0x2e]	38527	1			T10	1		T106	3		T8	5
valid_sources[0x2f]	39527	1			T106	1		T8	5		T98	3
valid_sources[0x30]	38545	1			T2	2		T8	6		T98	1
valid_sources[0x31]	39830	1			T8	3		T94	5		T9	4
valid_sources[0x32]	37653	1			T11	3		T8	6		T9	24
valid_sources[0x33]	40082	1			T4	1		T11	1		T106	1
valid_sources[0x34]	36477	1			T8	3		T97	1		T14	1056
valid_sources[0x35]	38160	1			T6	1		T7	1		T8	6
valid_sources[0x36]	39008	1			T2	1		T6	1		T58	1
valid_sources[0x37]	38283	1			T8	6		T338	1		T109	1
valid_sources[0x38]	38323	1			T6	1		T8	6		T110	1
valid_sources[0x39]	40773	1			T58	3		T8	8		T94	1
valid_sources[0x3a]	38999	1			T58	2		T8	1		T256	1
valid_sources[0x3b]	38823	1			T4	3		T8	7		T98	1
valid_sources[0x3c]	38100	1			T2	1		T11	4		T8	2
valid_sources[0x3d]	39267	1			T6	1		T106	4		T58	3
valid_sources[0x3e]	37673	1			T2	1		T106	2		T108	5
valid_sources[0x3f]	38092	1			T8	2		T65	3		T14	1089
valid_sources[0x40]	38979	1			T8	5		T65	6		T109	2
valid_sources[0x41]	38806	1			T2	2		T8	8		T97	1
valid_sources[0x42]	38478	1			T106	3		T8	5		T65	1
valid_sources[0x43]	38637	1			T8	3		T98	1		T9	7
valid_sources[0x44]	38045	1			T106	3		T58	1		T8	7
valid_sources[0x45]	37461	1			T6	2		T106	3		T58	1
valid_sources[0x46]	37968	1			T11	1		T108	2		T8	4
valid_sources[0x47]	38515	1			T4	1		T8	3		T97	1
valid_sources[0x48]	38401	1			T6	1		T8	1		T14	1107
valid_sources[0x49]	37795	1			T58	1		T8	8		T9	7
valid_sources[0x4a]	38493	1			T8	4		T9	17		T14	1102
valid_sources[0x4b]	36941	1			T2	1		T10	1		T58	2
valid_sources[0x4c]	38798	1			T10	1		T58	1		T8	3
valid_sources[0x4d]	38642	1			T8	3		T14	1100		T191	1
valid_sources[0x4e]	39391	1			T8	3		T9	15		T14	1049
valid_sources[0x4f]	38665	1			T11	1		T8	8		T9	2
valid_sources[0x50]	39880	1			T8	9		T9	16		T14	1027
valid_sources[0x51]	39783	1			T10	1		T106	4		T8	8
valid_sources[0x52]	38380	1			T10	1		T106	6		T58	1
valid_sources[0x53]	38745	1			T4	1		T106	1		T58	2
valid_sources[0x54]	39597	1			T8	10		T109	2		T14	1175
valid_sources[0x55]	39221	1			T4	2		T6	3		T8	7
valid_sources[0x56]	37076	1			T106	1		T58	2		T8	6
valid_sources[0x57]	38046	1			T2	1		T8	5		T96	3
valid_sources[0x58]	37698	1			T6	4		T7	2		T8	4
valid_sources[0x59]	38490	1			T2	1		T58	1		T8	8
valid_sources[0x5a]	38950	1			T10	1		T8	8		T9	2
valid_sources[0x5b]	39222	1			T30	80		T8	4		T96	3
valid_sources[0x5c]	37905	1			T2	1		T6	1		T58	4
valid_sources[0x5d]	40043	1			T2	1		T10	1		T58	2
valid_sources[0x5e]	40276	1			T58	1		T8	7		T9	19
valid_sources[0x5f]	39441	1			T106	1		T8	1		T65	5
valid_sources[0x60]	38061	1			T4	1		T112	60		T8	2
valid_sources[0x61]	38062	1			T10	1		T11	1		T8	1
valid_sources[0x62]	37549	1			T2	1		T8	2		T65	7
valid_sources[0x63]	39170	1			T7	1		T8	2		T96	2
valid_sources[0x64]	38304	1			T6	1		T8	7		T338	1
valid_sources[0x65]	39954	1			T5	20		T11	1		T8	9
valid_sources[0x66]	37911	1			T58	2		T8	6		T93	40
valid_sources[0x67]	37805	1			T106	7		T8	11		T9	6
valid_sources[0x68]	38100	1			T10	1		T8	5		T97	1
valid_sources[0x69]	37310	1			T8	3		T9	20		T256	1
valid_sources[0x6a]	40051	1			T58	1		T8	2		T256	1
valid_sources[0x6b]	38295	1			T10	1		T58	1		T8	7
valid_sources[0x6c]	38939	1			T10	1		T11	1		T58	2
valid_sources[0x6d]	39934	1			T11	1		T8	4		T256	1
valid_sources[0x6e]	37010	1			T13	1		T8	6		T150	2
valid_sources[0x6f]	39436	1			T2	1		T106	1		T8	5
valid_sources[0x70]	39191	1			T11	4		T14	1064		T191	1
valid_sources[0x71]	39643	1			T58	1		T8	3		T98	2
valid_sources[0x72]	38313	1			T7	1		T8	11		T65	2
valid_sources[0x73]	38420	1			T6	1		T58	1		T8	11
valid_sources[0x74]	39367	1			T58	3		T8	6		T109	1
valid_sources[0x75]	37299	1			T10	2		T6	1		T11	6
valid_sources[0x76]	38128	1			T10	1		T58	2		T8	3
valid_sources[0x77]	38195	1			T106	14		T7	1		T58	1
valid_sources[0x78]	39851	1			T4	7		T11	3		T8	3
valid_sources[0x79]	38592	1			T11	1		T106	2		T58	2
valid_sources[0x7a]	40689	1			T58	1		T8	3		T150	2
valid_sources[0x7b]	40036	1			T6	1		T106	1		T8	5
valid_sources[0x7c]	38939	1			T11	1		T106	1		T58	1
valid_sources[0x7d]	38705	1			T2	1		T106	11		T58	1
valid_sources[0x7e]	38384	1			T58	2		T8	6		T97	1
valid_sources[0x7f]	38541	1			T58	1		T8	6		T65	4
valid_sources[0x80]	37184	1			T2	1		T8	3		T65	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2441606

1

T2

20

T10

20

T4

30

values[0x0]

all_enables

biggest_size

3584868

1

T2

8

T10

9

T4

16

values[0x1]

all_enables

biggest_size

3585957

1

T2

12

T10

11

T4

14