Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

26780152

1

T1

986

T2

2698

T3

1012

full_word

8675163

1

T1

267

T2

996

T3

247

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35455035	1			T1	1253		T2	3694		T3	1259
auto[TlIntgErrCmd]	91	1			T272	3		T273	2		T274	4
auto[TlIntgErrData]	92	1			T272	3		T273	5		T274	10
auto[TlIntgErrBoth]	97	1			T272	4		T273	3		T274	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9863200

1

T1

943

T2

3390

T3

977

auto[1]

25592115

1

T1

310

T2

304

T3

282

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6208746	1			T1	803		T2	2528		T3	836
auto[TlIntgErrNone]	partial	auto[1]	20571148	1			T1	183		T2	170		T3	176
auto[TlIntgErrNone]	full_word	auto[0]	3654331	1			T1	140		T2	862		T3	141
auto[TlIntgErrNone]	full_word	auto[1]	5020810	1			T1	127		T2	134		T3	106
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T273	1		T274	2		T279	2
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T272	3		T273	1		T274	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T348	1		T278	1		T345	2
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T346	1		T351	1		T278	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T272	1		T273	5		T274	4
auto[TlIntgErrData]	partial	auto[1]	45	1			T272	2		T274	5		T279	8
auto[TlIntgErrData]	full_word	auto[0]	6	1			T279	2		T352	1		T353	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T274	1		T354	1		T355	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T272	1		T273	2		T274	1
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T272	3		T273	1		T274	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T350	1		T356	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T274	1		T346	1		T348	1