Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	464127747	8691055	0	0
check_regwen_rd_A	464127747	2785	0	0
check_timeout_rd_A	464127747	1841	0	0
check_trigger_regwen_rd_A	464127747	2727	0	0
consistency_check_period_rd_A	464127747	2920	0	0
creator_sw_cfg_read_lock_rd_A	464127747	1830	0	0
direct_access_address_rd_A	464127747	1868	0	0
direct_access_wdata_0_rd_A	464127747	1089	0	0
direct_access_wdata_1_rd_A	464127747	1341	0	0
integrity_check_period_rd_A	464127747	2664	0	0
intr_enable_rd_A	464127747	3395	0	0
owner_sw_cfg_read_lock_rd_A	464127747	1736	0	0
rot_creator_auth_codesign_read_lock_rd_A	464127747	1849	0	0
rot_creator_auth_state_read_lock_rd_A	464127747	1768	0	0
vendor_test_read_lock_rd_A	464127747	1706	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464127747	8691055	0	0
T14	117922	239114	0	0
T15	134132	18453	0	0
T16	0	43472	0	0
T18	0	166209	0	0
T19	0	59766	0	0
T40	0	154318	0	0
T51	13196	0	0	0
T100	71892	0	0	0
T144	14017	0	0	0
T188	32773	0	0	0
T191	18550	0	0	0
T202	12361	0	0	0
T220	0	119947	0	0
T238	20105	0	0	0
T252	0	278154	0	0
T280	0	72486	0	0
T281	0	168400	0	0
T282	12776	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464127747	2785	0	0
T15	134132	35	0	0
T21	0	220	0	0
T40	0	115	0	0
T111	37239	0	0	0
T171	18073	0	0	0
T172	14636	0	0	0
T188	32773	0	0	0
T189	12586	0	0	0
T192	28548	0	0	0
T214	22619	0	0	0
T215	22009	0	0	0
T261	0	58	0	0
T328	0	60	0	0
T329	0	64	0	0
T330	0	169	0	0
T331	0	40	0	0
T332	0	68	0	0
T333	0	68	0	0
T334	15016	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464127747	1841	0	0
T15	134132	40	0	0
T21	0	316	0	0
T40	0	141	0	0
T111	37239	0	0	0
T171	18073	0	0	0
T172	14636	0	0	0
T188	32773	0	0	0
T189	12586	0	0	0
T192	28548	0	0	0
T214	22619	0	0	0
T215	22009	0	0	0
T261	0	40	0	0
T328	0	73	0	0
T329	0	44	0	0
T330	0	172	0	0
T331	0	79	0	0
T332	0	63	0	0
T333	0	66	0	0
T334	15016	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464127747	2727	0	0
T15	134132	47	0	0
T21	0	253	0	0
T40	0	103	0	0
T111	37239	0	0	0
T171	18073	0	0	0
T172	14636	0	0	0
T188	32773	0	0	0
T189	12586	0	0	0
T192	28548	0	0	0
T214	22619	0	0	0
T215	22009	0	0	0
T261	0	25	0	0
T328	0	49	0	0
T329	0	64	0	0
T330	0	148	0	0
T331	0	60	0	0
T332	0	95	0	0
T333	0	43	0	0
T334	15016	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464127747	2920	0	0
T15	134132	40	0	0
T21	0	293	0	0
T40	0	122	0	0
T111	37239	0	0	0
T171	18073	0	0	0
T172	14636	0	0	0
T188	32773	0	0	0
T189	12586	0	0	0
T192	28548	0	0	0
T214	22619	0	0	0
T215	22009	0	0	0
T261	0	26	0	0
T328	0	58	0	0
T329	0	100	0	0
T330	0	148	0	0
T331	0	50	0	0
T332	0	118	0	0
T333	0	31	0	0
T334	15016	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464127747	1830	0	0
T15	134132	23	0	0
T21	0	275	0	0
T40	0	195	0	0
T111	37239	0	0	0
T171	18073	0	0	0
T172	14636	0	0	0
T188	32773	0	0	0
T189	12586	0	0	0
T192	28548	0	0	0
T214	22619	0	0	0
T215	22009	0	0	0
T261	0	66	0	0
T328	0	31	0	0
T329	0	60	0	0
T330	0	224	0	0
T331	0	93	0	0
T332	0	94	0	0
T333	0	25	0	0
T334	15016	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464127747	1868	0	0
T15	134132	38	0	0
T21	0	373	0	0
T40	0	191	0	0
T111	37239	0	0	0
T171	18073	0	0	0
T172	14636	0	0	0
T188	32773	0	0	0
T189	12586	0	0	0
T192	28548	0	0	0
T214	22619	0	0	0
T215	22009	0	0	0
T261	0	38	0	0
T328	0	51	0	0
T329	0	56	0	0
T330	0	118	0	0
T331	0	84	0	0
T332	0	180	0	0
T333	0	77	0	0
T334	15016	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464127747	1089	0	0
T15	134132	4	0	0
T21	0	189	0	0
T40	0	96	0	0
T111	37239	0	0	0
T171	18073	0	0	0
T172	14636	0	0	0
T188	32773	0	0	0
T189	12586	0	0	0
T192	28548	0	0	0
T214	22619	0	0	0
T215	22009	0	0	0
T261	0	18	0	0
T328	0	54	0	0
T329	0	32	0	0
T330	0	109	0	0
T331	0	53	0	0
T332	0	86	0	0
T333	0	23	0	0
T334	15016	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464127747	1341	0	0
T15	134132	17	0	0
T21	0	265	0	0
T40	0	163	0	0
T111	37239	0	0	0
T171	18073	0	0	0
T172	14636	0	0	0
T188	32773	0	0	0
T189	12586	0	0	0
T192	28548	0	0	0
T214	22619	0	0	0
T215	22009	0	0	0
T261	0	31	0	0
T328	0	37	0	0
T329	0	43	0	0
T330	0	110	0	0
T331	0	58	0	0
T332	0	81	0	0
T333	0	51	0	0
T334	15016	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464127747	2664	0	0
T15	134132	48	0	0
T21	0	220	0	0
T40	0	153	0	0
T111	37239	0	0	0
T171	18073	0	0	0
T172	14636	0	0	0
T188	32773	0	0	0
T189	12586	0	0	0
T192	28548	0	0	0
T214	22619	0	0	0
T215	22009	0	0	0
T261	0	21	0	0
T328	0	29	0	0
T329	0	69	0	0
T330	0	162	0	0
T331	0	92	0	0
T332	0	84	0	0
T333	0	33	0	0
T334	15016	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464127747	3395	0	0
T9	111822	25	0	0
T14	117922	0	0	0
T15	0	41	0	0
T21	0	277	0	0
T40	0	224	0	0
T50	11914	0	0	0
T51	13196	0	0	0
T57	13930	0	0	0
T99	108845	0	0	0
T109	25079	0	0	0
T110	85281	0	0	0
T144	14017	0	0	0
T186	0	37	0	0
T256	13049	0	0	0
T328	0	40	0	0
T329	0	83	0	0
T330	0	105	0	0
T335	0	28	0	0
T336	0	9	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464127747	1736	0	0
T15	134132	40	0	0
T21	0	232	0	0
T40	0	132	0	0
T111	37239	0	0	0
T171	18073	0	0	0
T172	14636	0	0	0
T188	32773	0	0	0
T189	12586	0	0	0
T192	28548	0	0	0
T214	22619	0	0	0
T215	22009	0	0	0
T261	0	52	0	0
T328	0	84	0	0
T329	0	48	0	0
T330	0	137	0	0
T331	0	102	0	0
T332	0	114	0	0
T333	0	44	0	0
T334	15016	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464127747	1849	0	0
T15	134132	49	0	0
T21	0	267	0	0
T40	0	162	0	0
T111	37239	0	0	0
T171	18073	0	0	0
T172	14636	0	0	0
T188	32773	0	0	0
T189	12586	0	0	0
T192	28548	0	0	0
T214	22619	0	0	0
T215	22009	0	0	0
T261	0	36	0	0
T328	0	45	0	0
T329	0	60	0	0
T330	0	173	0	0
T331	0	66	0	0
T332	0	119	0	0
T333	0	64	0	0
T334	15016	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464127747	1768	0	0
T15	134132	28	0	0
T21	0	334	0	0
T40	0	148	0	0
T111	37239	0	0	0
T171	18073	0	0	0
T172	14636	0	0	0
T188	32773	0	0	0
T189	12586	0	0	0
T192	28548	0	0	0
T214	22619	0	0	0
T215	22009	0	0	0
T261	0	37	0	0
T328	0	45	0	0
T329	0	60	0	0
T330	0	164	0	0
T331	0	58	0	0
T332	0	98	0	0
T333	0	49	0	0
T334	15016	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464127747	1706	0	0
T15	134132	33	0	0
T21	0	362	0	0
T40	0	132	0	0
T111	37239	0	0	0
T171	18073	0	0	0
T172	14636	0	0	0
T188	32773	0	0	0
T189	12586	0	0	0
T192	28548	0	0	0
T214	22619	0	0	0
T215	22009	0	0	0
T261	0	17	0	0
T328	0	39	0	0
T329	0	58	0	0
T330	0	122	0	0
T331	0	131	0	0
T332	0	74	0	0
T333	0	30	0	0
T334	15016	0	0	0