Module Definition
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Module : otp_ctrl_lfsr_timer
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.93 100.00 88.46 100.00 91.18 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_otp_ctrl_lfsr_timer 96.16 100.00 89.61 100.00 91.18 100.00



Module Instance : tb.dut.u_otp_ctrl_lfsr_timer

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.16 100.00 89.61 100.00 91.18 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.80 100.00 89.87 69.23 100.00 91.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.22 94.16 96.15 97.18 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_count_cnsty 80.80 80.80
u_prim_count_integ 80.80 80.80
u_prim_double_lfsr 87.95 100.00 100.00 51.81 100.00
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : otp_ctrl_lfsr_timer
Line No.TotalCoveredPercent
TOTAL9191100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14311100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN19011100.00
CONT_ASSIGN19111100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN20211100.00
CONT_ASSIGN24311100.00
ALWAYS2465252100.00
ALWAYS36733100.00
ALWAYS3701313100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
72 1 1
77 1 1
78 1 1
87 1 1
114 1 1
132 1 1
133 1 1
134 1 1
135 1 1
136 1 1
138 1 1
139 1 1
141 1 1
142 1 1
143 1 1
144 1 1
189 1 1
190 1 1
191 1 1
193 1 1
201 1 1
202 1 1
243 1 1
246 1 1
249 1 1
250 1 1
251 1 1
252 1 1
253 1 1
254 1 1
257 1 1
258 1 1
261 1 1
262 1 1
263 1 1
266 1 1
267 1 1
269 1 1
274 1 1
275 1 1
276 1 1
MISSING_ELSE
283 1 1
284 1 1
285 1 1
286 1 1
287 1 1
288 1 1
289 1 1
290 1 1
291 1 1
292 1 1
MISSING_ELSE
300 1 1
301 1 1
302 1 1
303 1 1
304 1 1
305 1 1
307 1 1
308 1 1
MISSING_ELSE
316 1 1
322 1 1
323 1 1
324 1 1
325 1 1
326 1 1
327 1 1
329 1 1
330 1 1
MISSING_ELSE
337 1 1
338 1 1
339 1 1
340 1 1
MISSING_ELSE
356 1 1
358 1 1
359 1 1
MISSING_ELSE
367 3 3
370 1 1
371 1 1
372 1 1
373 1 1
374 1 1
375 1 1
376 1 1
378 1 1
379 1 1
380 1 1
381 1 1
382 1 1
383 1 1


Cond Coverage for Module : otp_ctrl_lfsr_timer
TotalCoveredPercent
Conditions786988.46
Logical786988.46
Non-Logical00
Event00

 LINE       72
 EXPRESSION (reseed_en ? '0 : (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)))
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       72
 SUB-EXPRESSION (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       72
 SUB-EXPRESSION (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)
                 ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       78
 EXPRESSION (edn_req_o & edn_ack_i)
             ----1----   ----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       87
 EXPRESSION (reseed_en ? edn_data_i[(otp_ctrl_pkg::LfsrWidth - 1):0] : '0)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       101
 EXPRESSION (reseed_en || lfsr_en)
             ----1----    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       132
 EXPRESSION (timeout_i == '0)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       133
 EXPRESSION (integ_period_msk_i == '0)
            -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       134
 EXPRESSION (cnsty_period_msk_i == '0)
            -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       135
 EXPRESSION (integ_cnt == '0)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       136
 EXPRESSION (cnsty_cnt == '0)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 EXPRESSION (integ_set_period || integ_set_timeout)
             --------1-------    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T10,T4
10CoveredT2,T10,T4

 LINE       139
 EXPRESSION (cnsty_set_period || cnsty_set_timeout)
             --------1-------    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T13
10CoveredT2,T4,T13

 LINE       143
 EXPRESSION (integ_set_period ? ((lfsr_state & integ_mask)) : (40'(timeout_i)))
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T10,T4

 LINE       144
 EXPRESSION (cnsty_set_period ? ((lfsr_state & cnsty_mask)) : (40'(timeout_i)))
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T13

 LINE       167
 EXPRESSION (((!cnsty_cnt_zero)) && ((!cnsty_cnt_pause)))
             ---------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T9,T100
11CoveredT2,T4,T13

 LINE       191
 EXPRESSION (set_all_integ_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((integ_chk_req_q & (~integ_chk_ack_i))))
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T10,T4

 LINE       193
 EXPRESSION (set_all_cnsty_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((cnsty_chk_req_q & (~cnsty_chk_ack_i))))
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T13

 LINE       201
 EXPRESSION ((integ_chk_trig_q & ((~clr_integ_chk_trig))) | integ_chk_trig_i)
             ----------------------1---------------------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T10,T4
10Not Covered

 LINE       201
 SUB-EXPRESSION (integ_chk_trig_q & ((~clr_integ_chk_trig)))
                 --------1-------   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T10,T4
11Not Covered

 LINE       202
 EXPRESSION ((cnsty_chk_trig_q & ((~clr_cnsty_chk_trig))) | cnsty_chk_trig_i)
             ----------------------1---------------------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T10,T4
10CoveredT2,T4,T11

 LINE       202
 SUB-EXPRESSION (cnsty_chk_trig_q & ((~clr_cnsty_chk_trig)))
                 --------1-------   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T10,T4
11CoveredT2,T4,T11

 LINE       262
 EXPRESSION (cnsty_chk_trig_q || integ_chk_trig_q)
             --------1-------    --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT10,T4,T6
10CoveredT2,T10,T4

 LINE       283
 EXPRESSION ((((!integ_msk_zero)) && integ_cnt_zero) || integ_chk_trig_q)
             -------------------1-------------------    --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T10,T4
10CoveredT9,T14,T101

 LINE       283
 SUB-EXPRESSION (((!integ_msk_zero)) && integ_cnt_zero)
                 ---------1---------    -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T14,T101
11CoveredT9,T14,T101

 LINE       288
 EXPRESSION ((((!cnsty_msk_zero)) && cnsty_cnt_zero) || cnsty_chk_trig_q)
             -------------------1-------------------    --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T13
10CoveredT9,T14,T101

 LINE       288
 SUB-EXPRESSION (((!cnsty_msk_zero)) && cnsty_cnt_zero)
                 ---------1---------    -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T14,T101
11CoveredT9,T14,T101

 LINE       301
 EXPRESSION (((!timeout_zero)) && integ_cnt_zero)
             --------1--------    -------2------
-1--2-StatusTests
01CoveredT10,T112,T58
10CoveredT2,T4,T6
11CoveredT11,T65,T9

 LINE       304
 EXPRESSION (integ_chk_req_q == '0)
            -----------1-----------
-1-StatusTests
0CoveredT2,T10,T4
1CoveredT2,T10,T4

 LINE       323
 EXPRESSION (((!timeout_zero)) && cnsty_cnt_zero)
             --------1--------    -------2------
-1--2-StatusTests
01CoveredT112,T8,T9
10CoveredT2,T4,T13
11CoveredT58,T65,T9

 LINE       326
 EXPRESSION (cnsty_chk_req_q == '0)
            -----------1-----------
-1-StatusTests
0CoveredT2,T4,T13
1CoveredT2,T4,T13

FSM Coverage for Module : otp_ctrl_lfsr_timer
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 9 9 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
CnstyWaitSt 289 Covered T2,T4,T13
ErrorSt 302 Covered T10,T11,T106
IdleSt 275 Covered T1,T2,T3
IntegWaitSt 284 Covered T2,T10,T4
ResetSt 273 Covered T1,T2,T3


transitionsLine No.CoveredTests
CnstyWaitSt->ErrorSt 324 Covered T58,T65,T9
CnstyWaitSt->IdleSt 327 Covered T2,T4,T13
IdleSt->CnstyWaitSt 289 Covered T2,T4,T13
IdleSt->ErrorSt 358 Covered T10,T106,T9
IdleSt->IntegWaitSt 284 Covered T2,T10,T4
IntegWaitSt->ErrorSt 302 Covered T11,T65,T9
IntegWaitSt->IdleSt 305 Covered T2,T10,T4
ResetSt->ErrorSt 358 Covered T9,T191,T192
ResetSt->IdleSt 275 Covered T1,T2,T3



Branch Coverage for Module : otp_ctrl_lfsr_timer
Line No.TotalCoveredPercent
Branches 34 31 91.18
TERNARY 72 4 2 50.00
TERNARY 87 2 1 50.00
TERNARY 143 2 2 100.00
TERNARY 144 2 2 100.00
TERNARY 191 2 2 100.00
TERNARY 193 2 2 100.00
CASE 269 14 14 100.00
IF 356 2 2 100.00
IF 367 2 2 100.00
IF 370 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 72 (reseed_en) ? -2-: 72 (edn_req_o) ? -3-: 72 (lfsr_en) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 87 (reseed_en) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 143 (integ_set_period) ?

Branches:
-1-StatusTests
1 Covered T2,T10,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 144 (cnsty_set_period) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 (set_all_integ_reqs) ?

Branches:
-1-StatusTests
1 Covered T2,T10,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 193 (set_all_cnsty_reqs) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (state_q) -2-: 274 if (timer_en_i) -3-: 283 if ((((!integ_msk_zero) && integ_cnt_zero) || integ_chk_trig_q)) -4-: 288 if ((((!cnsty_msk_zero) && cnsty_cnt_zero) || cnsty_chk_trig_q)) -5-: 301 if (((!timeout_zero) && integ_cnt_zero)) -6-: 304 if ((integ_chk_req_q == '0)) -7-: 323 if (((!timeout_zero) && cnsty_cnt_zero)) -8-: 326 if ((cnsty_chk_req_q == '0)) -9-: 339 if ((!chk_timeout_q))

Branches:
-1--2--3--4--5--6--7--8--9-StatusTests
ResetSt 1 - - - - - - - Covered T1,T2,T3
ResetSt 0 - - - - - - - Covered T1,T2,T3
IdleSt - 1 - - - - - - Covered T2,T10,T4
IdleSt - 0 1 - - - - - Covered T2,T4,T13
IdleSt - 0 0 - - - - - Covered T1,T2,T3
IntegWaitSt - - - 1 - - - - Covered T11,T65,T9
IntegWaitSt - - - 0 1 - - - Covered T2,T10,T4
IntegWaitSt - - - 0 0 - - - Covered T2,T10,T4
CnstyWaitSt - - - - - 1 - - Covered T58,T65,T9
CnstyWaitSt - - - - - 0 1 - Covered T2,T4,T13
CnstyWaitSt - - - - - 0 0 - Covered T2,T4,T13
ErrorSt - - - - - - - 1 Covered T10,T106,T9
ErrorSt - - - - - - - 0 Covered T11,T58,T65
default - - - - - - - - Covered T23,T24,T25


LineNo. Expression -1-: 356 if ((((lfsr_err || integ_cnt_err) || cnsty_cnt_err) || lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)))

Branches:
-1-StatusTests
1 Covered T10,T106,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 367 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 370 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : otp_ctrl_lfsr_timer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 7 7 100.00 7 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 7 7 100.00 7 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ChkPendingKnown_A 461249151 460395867 0 0
ChkTimeoutKnown_A 461249151 460395867 0 0
CnstyChkReqKnown_A 461249151 460395867 0 0
EdnIsWideEnough_A 1148 1148 0 0
EdnReqKnown_A 461249151 460395867 0 0
IntegChkReqKnown_A 461249151 460395867 0 0
u_state_regs_A 461249151 460395867 0 0


ChkPendingKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461249151 460395867 0 0
T1 12692 12448 0 0
T2 18118 17780 0 0
T3 12299 12037 0 0
T4 27882 27333 0 0
T5 10391 10152 0 0
T6 52088 51396 0 0
T10 28147 27978 0 0
T11 97107 96443 0 0
T12 16199 15940 0 0
T13 48085 47265 0 0

ChkTimeoutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461249151 460395867 0 0
T1 12692 12448 0 0
T2 18118 17780 0 0
T3 12299 12037 0 0
T4 27882 27333 0 0
T5 10391 10152 0 0
T6 52088 51396 0 0
T10 28147 27978 0 0
T11 97107 96443 0 0
T12 16199 15940 0 0
T13 48085 47265 0 0

CnstyChkReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461249151 460395867 0 0
T1 12692 12448 0 0
T2 18118 17780 0 0
T3 12299 12037 0 0
T4 27882 27333 0 0
T5 10391 10152 0 0
T6 52088 51396 0 0
T10 28147 27978 0 0
T11 97107 96443 0 0
T12 16199 15940 0 0
T13 48085 47265 0 0

EdnIsWideEnough_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1148 1148 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

EdnReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461249151 460395867 0 0
T1 12692 12448 0 0
T2 18118 17780 0 0
T3 12299 12037 0 0
T4 27882 27333 0 0
T5 10391 10152 0 0
T6 52088 51396 0 0
T10 28147 27978 0 0
T11 97107 96443 0 0
T12 16199 15940 0 0
T13 48085 47265 0 0

IntegChkReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461249151 460395867 0 0
T1 12692 12448 0 0
T2 18118 17780 0 0
T3 12299 12037 0 0
T4 27882 27333 0 0
T5 10391 10152 0 0
T6 52088 51396 0 0
T10 28147 27978 0 0
T11 97107 96443 0 0
T12 16199 15940 0 0
T13 48085 47265 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461249151 460395867 0 0
T1 12692 12448 0 0
T2 18118 17780 0 0
T3 12299 12037 0 0
T4 27882 27333 0 0
T5 10391 10152 0 0
T6 52088 51396 0 0
T10 28147 27978 0 0
T11 97107 96443 0 0
T12 16199 15940 0 0
T13 48085 47265 0 0

Line Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer
Line No.TotalCoveredPercent
TOTAL9191100.00
CONT_ASSIGN7211100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN11411100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14311100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN19011100.00
CONT_ASSIGN19111100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN20211100.00
CONT_ASSIGN24311100.00
ALWAYS2465252100.00
ALWAYS36733100.00
ALWAYS3701313100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
72 1 1
77 1 1
78 1 1
87 1 1
114 1 1
132 1 1
133 1 1
134 1 1
135 1 1
136 1 1
138 1 1
139 1 1
141 1 1
142 1 1
143 1 1
144 1 1
189 1 1
190 1 1
191 1 1
193 1 1
201 1 1
202 1 1
243 1 1
246 1 1
249 1 1
250 1 1
251 1 1
252 1 1
253 1 1
254 1 1
257 1 1
258 1 1
261 1 1
262 1 1
263 1 1
266 1 1
267 1 1
269 1 1
274 1 1
275 1 1
276 1 1
MISSING_ELSE
283 1 1
284 1 1
285 1 1
286 1 1
287 1 1
288 1 1
289 1 1
290 1 1
291 1 1
292 1 1
MISSING_ELSE
300 1 1
301 1 1
302 1 1
303 1 1
304 1 1
305 1 1
307 1 1
308 1 1
MISSING_ELSE
316 1 1
322 1 1
323 1 1
324 1 1
325 1 1
326 1 1
327 1 1
329 1 1
330 1 1
MISSING_ELSE
337 1 1
338 1 1
339 1 1
340 1 1
MISSING_ELSE
356 1 1
358 1 1
359 1 1
MISSING_ELSE
367 3 3
370 1 1
371 1 1
372 1 1
373 1 1
374 1 1
375 1 1
376 1 1
378 1 1
379 1 1
380 1 1
381 1 1
382 1 1
383 1 1


Cond Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer
TotalCoveredPercent
Conditions776989.61
Logical776989.61
Non-Logical00
Event00

 LINE       72
 EXPRESSION (reseed_en ? '0 : (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)))
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       72
 SUB-EXPRESSION (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q))
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       72
 SUB-EXPRESSION (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)
                 ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       78
 EXPRESSION (edn_req_o & edn_ack_i)
             ----1----   ----2----
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Not Covered
11Not Covered

 LINE       87
 EXPRESSION (reseed_en ? edn_data_i[(otp_ctrl_pkg::LfsrWidth - 1):0] : '0)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       101
 EXPRESSION (reseed_en || lfsr_en)
             ----1----    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       132
 EXPRESSION (timeout_i == '0)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       133
 EXPRESSION (integ_period_msk_i == '0)
            -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       134
 EXPRESSION (cnsty_period_msk_i == '0)
            -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       135
 EXPRESSION (integ_cnt == '0)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       136
 EXPRESSION (cnsty_cnt == '0)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       138
 EXPRESSION (integ_set_period || integ_set_timeout)
             --------1-------    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T10,T4
10CoveredT2,T10,T4

 LINE       139
 EXPRESSION (cnsty_set_period || cnsty_set_timeout)
             --------1-------    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T13
10CoveredT2,T4,T13

 LINE       143
 EXPRESSION (integ_set_period ? ((lfsr_state & integ_mask)) : (40'(timeout_i)))
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T10,T4

 LINE       144
 EXPRESSION (cnsty_set_period ? ((lfsr_state & cnsty_mask)) : (40'(timeout_i)))
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T13

 LINE       167
 EXPRESSION (((!cnsty_cnt_zero)) && ((!cnsty_cnt_pause)))
             ---------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT8,T9,T100
11CoveredT2,T4,T13

 LINE       191
 EXPRESSION (set_all_integ_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((integ_chk_req_q & (~integ_chk_ack_i))))
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T10,T4

 LINE       193
 EXPRESSION (set_all_cnsty_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((cnsty_chk_req_q & (~cnsty_chk_ack_i))))
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T13

 LINE       201
 EXPRESSION ((integ_chk_trig_q & ((~clr_integ_chk_trig))) | integ_chk_trig_i)
             ----------------------1---------------------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T10,T4
10Not Covered

 LINE       201
 SUB-EXPRESSION (integ_chk_trig_q & ((~clr_integ_chk_trig)))
                 --------1-------   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T10,T4
11Not Covered

 LINE       202
 EXPRESSION ((cnsty_chk_trig_q & ((~clr_cnsty_chk_trig))) | cnsty_chk_trig_i)
             ----------------------1---------------------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T10,T4
10CoveredT2,T4,T11

 LINE       202
 SUB-EXPRESSION (cnsty_chk_trig_q & ((~clr_cnsty_chk_trig)))
                 --------1-------   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T10,T4
11CoveredT2,T4,T11

 LINE       262
 EXPRESSION (cnsty_chk_trig_q || integ_chk_trig_q)
             --------1-------    --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT10,T4,T6
10CoveredT2,T10,T4

 LINE       283
 EXPRESSION ((((!integ_msk_zero)) && integ_cnt_zero) || integ_chk_trig_q)
             -------------------1-------------------    --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T10,T4
10CoveredT9,T14,T101

 LINE       283
 SUB-EXPRESSION (((!integ_msk_zero)) && integ_cnt_zero)
                 ---------1---------    -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T14,T101
11CoveredT9,T14,T101

 LINE       288
 EXPRESSION ((((!cnsty_msk_zero)) && cnsty_cnt_zero) || cnsty_chk_trig_q)
             -------------------1-------------------    --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T13
10CoveredT9,T14,T101

 LINE       288
 SUB-EXPRESSION (((!cnsty_msk_zero)) && cnsty_cnt_zero)
                 ---------1---------    -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T14,T101
11CoveredT9,T14,T101

 LINE       301
 EXPRESSION (((!timeout_zero)) && integ_cnt_zero)
             --------1--------    -------2------
-1--2-StatusTests
01CoveredT10,T112,T58
10CoveredT2,T4,T6
11CoveredT11,T65,T9

 LINE       304
 EXPRESSION (integ_chk_req_q == '0)
            -----------1-----------
-1-StatusTests
0CoveredT2,T10,T4
1CoveredT2,T10,T4

 LINE       323
 EXPRESSION (((!timeout_zero)) && cnsty_cnt_zero)
             --------1--------    -------2------
-1--2-StatusTests
01CoveredT112,T8,T9
10CoveredT2,T4,T13
11CoveredT58,T65,T9

 LINE       326
 EXPRESSION (cnsty_chk_req_q == '0)
            -----------1-----------
-1-StatusTests
0CoveredT2,T4,T13
1CoveredT2,T4,T13

FSM Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 9 9 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
CnstyWaitSt 289 Covered T2,T4,T13
ErrorSt 302 Covered T10,T11,T106
IdleSt 275 Covered T1,T2,T3
IntegWaitSt 284 Covered T2,T10,T4
ResetSt 273 Covered T1,T2,T3


transitionsLine No.CoveredTests
CnstyWaitSt->ErrorSt 324 Covered T58,T65,T9
CnstyWaitSt->IdleSt 327 Covered T2,T4,T13
IdleSt->CnstyWaitSt 289 Covered T2,T4,T13
IdleSt->ErrorSt 358 Covered T10,T106,T9
IdleSt->IntegWaitSt 284 Covered T2,T10,T4
IntegWaitSt->ErrorSt 302 Covered T11,T65,T9
IntegWaitSt->IdleSt 305 Covered T2,T10,T4
ResetSt->ErrorSt 358 Covered T9,T191,T192
ResetSt->IdleSt 275 Covered T1,T2,T3



Branch Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer
Line No.TotalCoveredPercent
Branches 34 31 91.18
TERNARY 72 4 2 50.00
TERNARY 87 2 1 50.00
TERNARY 143 2 2 100.00
TERNARY 144 2 2 100.00
TERNARY 191 2 2 100.00
TERNARY 193 2 2 100.00
CASE 269 14 14 100.00
IF 356 2 2 100.00
IF 367 2 2 100.00
IF 370 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 72 (reseed_en) ? -2-: 72 (edn_req_o) ? -3-: 72 (lfsr_en) ?

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 87 (reseed_en) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 143 (integ_set_period) ?

Branches:
-1-StatusTests
1 Covered T2,T10,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 144 (cnsty_set_period) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 191 (set_all_integ_reqs) ?

Branches:
-1-StatusTests
1 Covered T2,T10,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 193 (set_all_cnsty_reqs) ?

Branches:
-1-StatusTests
1 Covered T2,T4,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 269 case (state_q) -2-: 274 if (timer_en_i) -3-: 283 if ((((!integ_msk_zero) && integ_cnt_zero) || integ_chk_trig_q)) -4-: 288 if ((((!cnsty_msk_zero) && cnsty_cnt_zero) || cnsty_chk_trig_q)) -5-: 301 if (((!timeout_zero) && integ_cnt_zero)) -6-: 304 if ((integ_chk_req_q == '0)) -7-: 323 if (((!timeout_zero) && cnsty_cnt_zero)) -8-: 326 if ((cnsty_chk_req_q == '0)) -9-: 339 if ((!chk_timeout_q))

Branches:
-1--2--3--4--5--6--7--8--9-StatusTests
ResetSt 1 - - - - - - - Covered T1,T2,T3
ResetSt 0 - - - - - - - Covered T1,T2,T3
IdleSt - 1 - - - - - - Covered T2,T10,T4
IdleSt - 0 1 - - - - - Covered T2,T4,T13
IdleSt - 0 0 - - - - - Covered T1,T2,T3
IntegWaitSt - - - 1 - - - - Covered T11,T65,T9
IntegWaitSt - - - 0 1 - - - Covered T2,T10,T4
IntegWaitSt - - - 0 0 - - - Covered T2,T10,T4
CnstyWaitSt - - - - - 1 - - Covered T58,T65,T9
CnstyWaitSt - - - - - 0 1 - Covered T2,T4,T13
CnstyWaitSt - - - - - 0 0 - Covered T2,T4,T13
ErrorSt - - - - - - - 1 Covered T10,T106,T9
ErrorSt - - - - - - - 0 Covered T11,T58,T65
default - - - - - - - - Covered T23,T24,T25


LineNo. Expression -1-: 356 if ((((lfsr_err || integ_cnt_err) || cnsty_cnt_err) || lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)))

Branches:
-1-StatusTests
1 Covered T10,T106,T9
0 Covered T1,T2,T3


LineNo. Expression -1-: 367 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 370 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_otp_ctrl_lfsr_timer
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 7 7 100.00 7 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 7 7 100.00 7 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ChkPendingKnown_A 461249151 460395867 0 0
ChkTimeoutKnown_A 461249151 460395867 0 0
CnstyChkReqKnown_A 461249151 460395867 0 0
EdnIsWideEnough_A 1148 1148 0 0
EdnReqKnown_A 461249151 460395867 0 0
IntegChkReqKnown_A 461249151 460395867 0 0
u_state_regs_A 461249151 460395867 0 0


ChkPendingKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461249151 460395867 0 0
T1 12692 12448 0 0
T2 18118 17780 0 0
T3 12299 12037 0 0
T4 27882 27333 0 0
T5 10391 10152 0 0
T6 52088 51396 0 0
T10 28147 27978 0 0
T11 97107 96443 0 0
T12 16199 15940 0 0
T13 48085 47265 0 0

ChkTimeoutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461249151 460395867 0 0
T1 12692 12448 0 0
T2 18118 17780 0 0
T3 12299 12037 0 0
T4 27882 27333 0 0
T5 10391 10152 0 0
T6 52088 51396 0 0
T10 28147 27978 0 0
T11 97107 96443 0 0
T12 16199 15940 0 0
T13 48085 47265 0 0

CnstyChkReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461249151 460395867 0 0
T1 12692 12448 0 0
T2 18118 17780 0 0
T3 12299 12037 0 0
T4 27882 27333 0 0
T5 10391 10152 0 0
T6 52088 51396 0 0
T10 28147 27978 0 0
T11 97107 96443 0 0
T12 16199 15940 0 0
T13 48085 47265 0 0

EdnIsWideEnough_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1148 1148 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

EdnReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461249151 460395867 0 0
T1 12692 12448 0 0
T2 18118 17780 0 0
T3 12299 12037 0 0
T4 27882 27333 0 0
T5 10391 10152 0 0
T6 52088 51396 0 0
T10 28147 27978 0 0
T11 97107 96443 0 0
T12 16199 15940 0 0
T13 48085 47265 0 0

IntegChkReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461249151 460395867 0 0
T1 12692 12448 0 0
T2 18118 17780 0 0
T3 12299 12037 0 0
T4 27882 27333 0 0
T5 10391 10152 0 0
T6 52088 51396 0 0
T10 28147 27978 0 0
T11 97107 96443 0 0
T12 16199 15940 0 0
T13 48085 47265 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 461249151 460395867 0 0
T1 12692 12448 0 0
T2 18118 17780 0 0
T3 12299 12037 0 0
T4 27882 27333 0 0
T5 10391 10152 0 0
T6 52088 51396 0 0
T10 28147 27978 0 0
T11 97107 96443 0 0
T12 16199 15940 0 0
T13 48085 47265 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%