Unified Coverage Report :: Module Instance :: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.23	100.00	100.00		90.00	100.00	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.56	100.00	100.00	100.00	90.00	98.15	97.22

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.32	100.00	100.00	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.75	100.00	97.06		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.83	100.00	97.06	100.00	91.67	98.25	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.18		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_ecc_reg.u_otp_ctrl_ecc_reg	95.00	100.00		100.00		80.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		86	86	100.00
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	61	61	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
224		excluded
			Exclude Annotation: VC_COV_UNR
225		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
276		excluded
			Exclude Annotation: VC_COV_UNR
277		excluded
			Exclude Annotation: VC_COV_UNR
279		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Covered	T1,T2,T3
1	Excluded		VC_COV_UNR

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T72,T142,T143
1	Covered	T72,T142,T143

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T3,T10

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T4
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T11

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T11

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T3,T10
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T3,T10
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T190
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T9,T191,T192
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T4,T11
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Not Covered
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T72,T73,T74
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests	Exclude Annotation
AccessError	256	Covered	T2,T4,T11
CheckFailError	317	Covered	T72,T142,T143
FsmStateError	289	Covered	T1,T3,T10
MacroEccCorrError	221	Excluded		VC_COV_UNR
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded
AccessError->FsmStateError	325	Covered	T106,T8,T9
AccessError->MacroEccCorrError	221	Excluded
AccessError->NoError	235	Covered	T2,T4,T11
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded
CheckFailError->NoError	235	Covered	T72,T142,T143
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded
FsmStateError->NoError	235	Covered	T1,T3,T10
MacroEccCorrError->AccessError	256	Excluded
MacroEccCorrError->CheckFailError	317	Excluded
MacroEccCorrError->FsmStateError	325	Excluded
MacroEccCorrError->NoError	235	Excluded
NoError->AccessError	256	Covered	T2,T4,T11
NoError->CheckFailError	317	Covered	T72,T142,T143
NoError->FsmStateError	289	Covered	T1,T3,T10
NoError->MacroEccCorrError	221	Excluded

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	18	18	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests	Exclude Annotation
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T8,T9,T100
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T4,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Excluded		VC_COV_UNR
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T3,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T10,T6,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T10,T6,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T3,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T72,T142,T143
1	0	Covered	T72,T142,T143
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T10
1	0	Covered	T1,T3,T10
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	461249151	460395867	0	0
DigestKnown_A	461249151	460395867	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	461249151	12760	0	0
ErrorKnown_A	461249151	460395867	0	0
FsmStateKnown_A	461249151	460395867	0	0
InitDoneKnown_A	461249151	460395867	0	0
InitReadLocksPartition_A	461249151	101937096	0	0
InitWriteLocksPartition_A	461249151	101937096	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	461249151	460395867	0	0
OtpCmdKnown_A	461249151	460395867	0	0
OtpErrorState_A	461249151	0	0	0
OtpReqKnown_A	461249151	460395867	0	0
OtpSizeKnown_A	461249151	460395867	0	0
OtpWdataKnown_A	461249151	460395867	0	0
ReadLockPropagation_A	461249151	223083759	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	461249151	460395867	0	0
TlulRdataKnown_A	461249151	460395867	0	0
TlulReadOnReadLock_A	461249151	7897	0	0
TlulRerrorKnown_A	461249151	460395867	0	0
TlulRvalidKnown_A	461249151	460395867	0	0
WriteLockPropagation_A	461249151	2014369	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	461249151	23724044	0	0
u_state_regs_A	461249151	460395867	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	12760	0	0
T72	8425	2736	0	0
T142	0	3767	0	0
T143	0	2572	0	0
T152	0	3685	0	0
T153	31603	0	0	0
T154	75986	0	0	0
T155	14839	0	0	0
T156	10534	0	0	0
T157	10351	0	0	0
T158	42330	0	0	0
T159	55688	0	0	0
T160	40381	0	0	0
T161	15240	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	101937096	0	0
T1	12692	5044	0	0
T2	18118	473	0	0
T3	12299	3995	0	0
T4	27882	819	0	0
T5	10391	1458	0	0
T6	52088	20514	0	0
T10	28147	11369	0	0
T11	97107	18496	0	0
T12	16199	3534	0	0
T13	48085	550	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	101937096	0	0
T1	12692	5044	0	0
T2	18118	473	0	0
T3	12299	3995	0	0
T4	27882	819	0	0
T5	10391	1458	0	0
T6	52088	20514	0	0
T10	28147	11369	0	0
T11	97107	18496	0	0
T12	16199	3534	0	0
T13	48085	550	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	223083759	0	0
T2	18118	2740	0	0
T3	12299	0	0	0
T4	27882	1116	0	0
T5	10391	0	0	0
T6	52088	0	0	0
T7	0	61436	0	0
T10	28147	10280	0	0
T11	97107	18792	0	0
T12	16199	0	0	0
T13	48085	12973	0	0
T17	0	10372	0	0
T30	0	10214	0	0
T41	0	38717	0	0
T106	50219	36121	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	7897	0	0
T2	18118	2	0	0
T3	12299	0	0	0
T4	27882	2	0	0
T5	10391	0	0	0
T6	52088	10	0	0
T7	0	7	0	0
T10	28147	4	0	0
T11	97107	8	0	0
T12	16199	0	0	0
T13	48085	6	0	0
T17	0	13	0	0
T30	0	8	0	0
T106	50219	9	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	2014369	0	0
T8	947410	52383	0	0
T9	0	48386	0	0
T17	95044	10248	0	0
T30	39493	3063	0	0
T41	95027	9598	0	0
T49	16153	0	0	0
T55	19385	0	0	0
T58	48292	0	0	0
T66	15662	0	0	0
T100	0	5315	0	0
T101	0	3215	0	0
T102	0	7790	0	0
T103	0	77545	0	0
T104	0	2670	0	0
T108	32387	0	0	0
T112	28662	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	23724044	0	0
T2	18118	11143	0	0
T3	12299	2938	0	0
T4	27882	0	0	0
T5	10391	0	0	0
T6	52088	0	0	0
T8	0	474197	0	0
T10	28147	0	0	0
T11	97107	73555	0	0
T12	16199	0	0	0
T13	48085	37133	0	0
T17	0	83240	0	0
T30	0	29599	0	0
T41	0	77378	0	0
T65	0	15634	0	0
T106	50219	0	0	0
T150	0	7551	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T66,T144

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T6,T95,T65

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T74,T145,T146
1	Covered	T74,T145,T146

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T3,T10

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T6
1	1	Covered	T1,T3,T4

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T4

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T4

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T3,T10
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T3,T4
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T3,T10
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T9,T191,T192
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T172,T173,T175
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T10,T11
ReadSt->ReadWaitSt	252	Covered	T1,T3,T4
ReadWaitSt->ErrorSt	276	Covered	T112,T193,T194
ReadWaitSt->IdleSt	270	Covered	T1,T3,T4
ResetSt->ErrorSt	315	Covered	T72,T73,T74
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T10,T11
CheckFailError	317	Covered	T74,T145,T146
FsmStateError	289	Covered	T1,T3,T10
MacroEccCorrError	221	Covered	T1,T6,T66
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T10,T106,T8
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T10,T11
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T74,T145,T146
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T3,T10
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T1,T6,T66
MacroEccCorrError->NoError	235	Covered	T65,T59,T31
NoError->AccessError	256	Covered	T2,T10,T11
NoError->CheckFailError	317	Covered	T74,T145,T146
NoError->FsmStateError	289	Covered	T3,T6,T11
NoError->MacroEccCorrError	221	Covered	T1,T6,T66

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T1,T66,T144
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T172,T173,T175
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T4
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T8,T9,T100
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T10,T11
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T6,T95,T65
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T112,T193,T194
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T3,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T10,T6,T106
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T10,T6,T106
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T3,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T74,T145,T146
1	0	Covered	T74,T145,T146
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T10
1	0	Covered	T1,T3,T10
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	461249151	460395867	0	0
DigestKnown_A	461249151	460395867	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	461249151	16446	0	0
ErrorKnown_A	461249151	460395867	0	0
FsmStateKnown_A	461249151	460395867	0	0
InitDoneKnown_A	461249151	460395867	0	0
InitReadLocksPartition_A	461249151	102117272	0	0
InitWriteLocksPartition_A	461249151	102117272	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	461249151	460395867	0	0
OtpCmdKnown_A	461249151	460395867	0	0
OtpErrorState_A	461249151	72	0	0
OtpReqKnown_A	461249151	460395867	0	0
OtpSizeKnown_A	461249151	460395867	0	0
OtpWdataKnown_A	461249151	460395867	0	0
ReadLockPropagation_A	461249151	207654288	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	461249151	460395867	0	0
TlulRdataKnown_A	461249151	460395867	0	0
TlulReadOnReadLock_A	461249151	8218	0	0
TlulRerrorKnown_A	461249151	460395867	0	0
TlulRvalidKnown_A	461249151	460395867	0	0
WriteLockPropagation_A	461249151	2030633	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	461249151	23505035	0	0
u_state_regs_A	461249151	460395867	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	16446	0	0
T74	10437	3048	0	0
T143	0	2572	0	0
T145	0	3722	0	0
T146	0	3382	0	0
T151	0	3722	0	0
T162	50787	0	0	0
T163	14497	0	0	0
T164	49693	0	0	0
T165	12916	0	0	0
T166	23530	0	0	0
T167	62056	0	0	0
T168	10461	0	0	0
T169	21918	0	0	0
T170	14057	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	102117272	0	0
T1	12692	5095	0	0
T2	18118	541	0	0
T3	12299	4046	0	0
T4	27882	955	0	0
T5	10391	1492	0	0
T6	52088	20667	0	0
T10	28147	11420	0	0
T11	97107	18649	0	0
T12	16199	3585	0	0
T13	48085	703	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	102117272	0	0
T1	12692	5095	0	0
T2	18118	541	0	0
T3	12299	4046	0	0
T4	27882	955	0	0
T5	10391	1492	0	0
T6	52088	20667	0	0
T10	28147	11420	0	0
T11	97107	18649	0	0
T12	16199	3585	0	0
T13	48085	703	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	72	0	0
T8	947410	0	0	0
T49	16153	0	0	0
T55	19385	0	0	0
T56	13650	0	0	0
T58	48292	0	0	0
T66	15662	0	0	0
T93	27460	0	0	0
T94	23561	0	0	0
T95	107631	0	0	0
T112	28662	1	0	0
T161	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T179	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	207654288	0	0
T2	18118	4592	0	0
T3	12299	0	0	0
T4	27882	3343	0	0
T5	10391	0	0	0
T6	52088	0	0	0
T8	0	190227	0	0
T10	28147	15507	0	0
T11	97107	12741	0	0
T12	16199	0	0	0
T13	48085	10259	0	0
T17	0	9512	0	0
T30	0	10315	0	0
T41	0	47560	0	0
T106	50219	38673	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	8218	0	0
T2	18118	2	0	0
T3	12299	0	0	0
T4	27882	0	0	0
T5	10391	0	0	0
T6	52088	3	0	0
T7	0	10	0	0
T10	28147	5	0	0
T11	97107	3	0	0
T12	16199	0	0	0
T13	48085	8	0	0
T17	0	5	0	0
T30	0	7	0	0
T41	0	3	0	0
T106	50219	11	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	2030633	0	0
T2	18118	3133	0	0
T3	12299	0	0	0
T4	27882	0	0	0
T5	10391	0	0	0
T6	52088	0	0	0
T8	0	53369	0	0
T9	0	49133	0	0
T10	28147	0	0	0
T11	97107	28364	0	0
T12	16199	0	0	0
T13	48085	4110	0	0
T17	0	14667	0	0
T30	0	5943	0	0
T41	0	28116	0	0
T99	0	7840	0	0
T106	50219	0	0	0
T110	0	6028	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	23505035	0	0
T2	18118	11109	0	0
T3	12299	0	0	0
T4	27882	11768	0	0
T5	10391	0	0	0
T6	52088	0	0	0
T10	28147	2940	0	0
T11	97107	73436	0	0
T12	16199	0	0	0
T13	48085	36997	0	0
T17	0	83070	0	0
T30	0	29514	0	0
T41	0	77225	0	0
T106	50219	2907	0	0
T107	0	13755	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T66,T147,T26

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T95,T59

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T23,T24,T25

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T73,T142,T146
1	Covered	T73,T142,T146

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T10,T6

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T4
1	1	Covered	T1,T2,T3

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T1,T3,T10
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T2,T3
ReadWaitSt	252	Covered	T1,T2,T3
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->ErrorSt	315	Covered	T1,T10,T6
IdleSt->ReadSt	236	Covered	T1,T2,T3
InitSt->ErrorSt	315	Covered	T9,T191,T192
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T3,T116,T171
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T2,T10,T4
ReadSt->ReadWaitSt	252	Covered	T1,T2,T3
ReadWaitSt->ErrorSt	276	Covered	T149,T181,T182
ReadWaitSt->IdleSt	270	Covered	T1,T2,T3
ResetSt->ErrorSt	315	Covered	T72,T73,T74
ResetSt->IdleSt	196	Excluded		VC_COV_UNR
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T2,T10,T4
CheckFailError	317	Covered	T73,T142,T146
FsmStateError	289	Covered	T1,T10,T6
MacroEccCorrError	221	Covered	T11,T66,T95
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	317	Excluded		VC_COV_UNR
AccessError->FsmStateError	325	Covered	T10,T8,T9
AccessError->MacroEccCorrError	221	Excluded		VC_COV_UNR
AccessError->NoError	235	Covered	T2,T4,T11
CheckFailError->AccessError	256	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	325	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	221	Excluded		VC_COV_UNR
CheckFailError->NoError	235	Covered	T73,T142,T146
FsmStateError->AccessError	256	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	317	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	221	Excluded		VC_COV_UNR
FsmStateError->NoError	235	Covered	T1,T10,T6
MacroEccCorrError->AccessError	256	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T66,T95,T147
MacroEccCorrError->NoError	235	Covered	T11,T59,T31
NoError->AccessError	256	Covered	T2,T10,T4
NoError->CheckFailError	317	Covered	T73,T142,T146
NoError->FsmStateError	289	Covered	T1,T6,T11
NoError->MacroEccCorrError	221	Covered	T11,T66,T95

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T66,T147,T26
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T3,T116,T171
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T8,T9,T100
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T2,T10,T4
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T11,T95,T59
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T149,T181,T182
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T3,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T10,T6,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T10,T6,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T3,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T23,T24,T25

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T73,T142,T146
1	0	Covered	T73,T142,T146
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T10,T6
1	0	Covered	T1,T3,T10
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	461249151	460395867	0	0
DigestKnown_A	461249151	460395867	0	0
DigestOffsetMustBeRepresentable_A	1148	1148	0	0
EccErrorState_A	461249151	10876	0	0
ErrorKnown_A	461249151	460395867	0	0
FsmStateKnown_A	461249151	460395867	0	0
InitDoneKnown_A	461249151	460395867	0	0
InitReadLocksPartition_A	461249151	102296093	0	0
InitWriteLocksPartition_A	461249151	102296093	0	0
OffsetMustBeBlockAligned_A	1148	1148	0	0
OtpAddrKnown_A	461249151	460395867	0	0
OtpCmdKnown_A	461249151	460395867	0	0
OtpErrorState_A	461249151	51	0	0
OtpReqKnown_A	461249151	460395867	0	0
OtpSizeKnown_A	461249151	460395867	0	0
OtpWdataKnown_A	461249151	460395867	0	0
ReadLockPropagation_A	461249151	228165667	0	0
SizeMustBeBlockAligned_A	1148	1148	0	0
TlulGntKnown_A	461249151	460395867	0	0
TlulRdataKnown_A	461249151	460395867	0	0
TlulReadOnReadLock_A	461249151	8318	0	0
TlulRerrorKnown_A	461249151	460395867	0	0
TlulRvalidKnown_A	461249151	460395867	0	0
WriteLockPropagation_A	461249151	1308021	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	461249151	15313622	0	0
u_state_regs_A	461249151	460395867	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	10876	0	0
T71	23707	0	0	0
T73	12141	3727	0	0
T75	166224	0	0	0
T79	16320	0	0	0
T142	0	3767	0	0
T146	0	3382	0	0
T180	13440	0	0	0
T195	46498	0	0	0
T196	11655	0	0	0
T197	53198	0	0	0
T198	38874	0	0	0
T199	28760	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	102296093	0	0
T1	12692	5146	0	0
T2	18118	609	0	0
T3	12299	4087	0	0
T4	27882	1091	0	0
T5	10391	1526	0	0
T6	52088	20820	0	0
T10	28147	11471	0	0
T11	97107	18802	0	0
T12	16199	3636	0	0
T13	48085	856	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	102296093	0	0
T1	12692	5146	0	0
T2	18118	609	0	0
T3	12299	4087	0	0
T4	27882	1091	0	0
T5	10391	1526	0	0
T6	52088	20820	0	0
T10	28147	11471	0	0
T11	97107	18802	0	0
T12	16199	3636	0	0
T13	48085	856	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	51	0	0
T3	12299	1	0	0
T4	27882	0	0	0
T5	10391	0	0	0
T6	52088	0	0	0
T7	77506	0	0	0
T10	28147	0	0	0
T11	97107	0	0	0
T12	16199	0	0	0
T13	48085	0	0	0
T106	50219	0	0	0
T116	0	1	0	0
T149	0	1	0	0
T171	0	1	0	0
T174	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	228165667	0	0
T2	18118	3127	0	0
T3	12299	0	0	0
T4	27882	1112	0	0
T5	10391	0	0	0
T6	52088	0	0	0
T7	0	61432	0	0
T10	28147	12665	0	0
T11	97107	13100	0	0
T12	16199	0	0	0
T13	48085	7928	0	0
T17	0	11096	0	0
T30	0	11024	0	0
T41	0	53735	0	0
T106	50219	0	0	0
T107	0	364	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1148	1148	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	8318	0	0
T2	18118	2	0	0
T3	12299	0	0	0
T4	27882	1	0	0
T5	10391	0	0	0
T6	52088	8	0	0
T7	0	16	0	0
T10	28147	3	0	0
T11	97107	6	0	0
T12	16199	0	0	0
T13	48085	3	0	0
T17	0	7	0	0
T30	0	7	0	0
T106	50219	15	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	1308021	0	0
T8	947410	61788	0	0
T17	95044	4870	0	0
T41	95027	0	0	0
T49	16153	0	0	0
T55	19385	0	0	0
T58	48292	0	0	0
T59	0	6604	0	0
T66	15662	0	0	0
T93	27460	0	0	0
T94	23561	0	0	0
T100	0	4740	0	0
T102	0	3062	0	0
T103	0	63681	0	0
T105	0	1316	0	0
T112	28662	0	0	0
T128	0	3234	0	0
T186	0	43455	0	0
T187	0	3125	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	15313622	0	0
T2	18118	11075	0	0
T3	12299	2916	0	0
T4	27882	11700	0	0
T5	10391	0	0	0
T6	52088	0	0	0
T8	0	332936	0	0
T10	28147	2923	0	0
T11	97107	73317	0	0
T12	16199	0	0	0
T13	48085	36861	0	0
T17	0	82900	0	0
T30	0	29429	0	0
T106	50219	0	0	0
T112	0	19324	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461249151	460395867	0	0
T1	12692	12448	0	0
T2	18118	17780	0	0
T3	12299	12037	0	0
T4	27882	27333	0	0
T5	10391	10152	0	0
T6	52088	51396	0	0
T10	28147	27978	0	0
T11	97107	96443	0	0
T12	16199	15940	0	0
T13	48085	47265	0	0