Unified Coverage Report :: Module Instance :: tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4.wr_en_data_arb

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	83.33	100.00			100.00		u_csr3_field4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	83.33	100.00			100.00		u_csr3_field5

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	83.33	100.00			100.00		u_csr3_field6

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	83.33	100.00			100.00		u_csr3_field7

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	83.33	100.00			100.00		u_csr3_field8

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_csr4_field0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_csr4_field1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_csr4_field2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_csr4_field3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_csr5_field0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_csr5_field1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	83.33	100.00			100.00		u_csr5_field2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	83.33	100.00			100.00		u_csr5_field3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	83.33	100.00			100.00		u_csr5_field4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	83.33	100.00			100.00		u_csr5_field5

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_csr5_field6

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field4.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	43	1	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	0	1
44	0	1
51		unreachable
52		unreachable
53		unreachable

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field5.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	43	1	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	0	1
44	0	1
51		unreachable
52		unreachable
53		unreachable

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field6.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	43	1	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	0	1
44	0	1
51		unreachable
52		unreachable
53		unreachable

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field7.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	43	1	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	0	1
44	0	1
51		unreachable
52		unreachable
53		unreachable

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr3_field8.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	43	1	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	0	1
44	0	1
51		unreachable
52		unreachable
53		unreachable

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

---

Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T2,T17,T8

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T8

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T8

---

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field0.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	34	((we == 1'b1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T17,T8
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

---

Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T2,T17,T8

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T8

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T8

---

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field1.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	34	((we == 1'b1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T17,T8
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

---

Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T2,T17,T8

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T8

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T8

---

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field2.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	34	((we == 1'b1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T17,T8
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

---

Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T2,T17,T8

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T8

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T8

---

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr4_field3.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	34	((we == 1'b1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T17,T8
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

---

Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
1	0	Covered	T2,T17,T8

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T8

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T8

---

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field0.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	34	((we == 1'b1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T17,T8
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

---

Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
1	0	Covered	T2,T17,T8

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T8

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T8

---

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field1.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	34	((we == 1'b1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T17,T8
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field2.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	43	1	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	0	1
44	0	1
51		unreachable
52		unreachable
53		unreachable

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field3.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	43	1	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	0	1
44	0	1
51		unreachable
52		unreachable
53		unreachable

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field4.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	43	1	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	0	1
44	0	1
51		unreachable
52		unreachable
53		unreachable

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field5.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	43	1	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	51	0	0
CONT_ASSIGN	52	0	0
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43	0	1
44	0	1
51		unreachable
52		unreachable
53		unreachable

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

---

Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Excluded		VC_COV_UNR
1	0	Covered	T2,T17,T8

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T8

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T8

---

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_csr5_field6.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	34	((we == 1'b1)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T17,T8
0	Covered	T1,T2,T3