Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25669036

1

T1

2408

T2

915

T3

1138

full_word

8296513

1

T1

1898

T2

572

T3

1006

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33965229	1			T1	4306		T2	1487		T3	2144
auto[TlIntgErrCmd]	111	1			T253	9		T254	4		T255	4
auto[TlIntgErrData]	103	1			T253	6		T254	7		T255	9
auto[TlIntgErrBoth]	106	1			T253	5		T254	9		T255	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9652159

1

T1

3844

T2

1317

T3

1821

auto[1]

24313390

1

T1

462

T2

170

T3

323

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6143174	1			T1	2129		T2	822		T3	956
auto[TlIntgErrNone]	partial	auto[1]	19525571	1			T1	279		T2	93		T3	182
auto[TlIntgErrNone]	full_word	auto[0]	3508848	1			T1	1715		T2	495		T3	865
auto[TlIntgErrNone]	full_word	auto[1]	4787636	1			T1	183		T2	77		T3	141
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T253	2		T254	2		T255	2
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T253	6		T254	1		T255	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T253	1		T262	1		T369	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T254	1		T368	1		T362	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T253	3		T254	2		T255	4
auto[TlIntgErrData]	partial	auto[1]	47	1			T253	3		T254	4		T255	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T254	1		T255	1		T361	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T367	2		T368	1		T362	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T253	3		T254	2		T255	2
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T253	2		T254	5		T255	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T254	1		T367	1		T368	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T254	1		T367	1		T363	1