Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.34	94.81	96.15	97.14		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	491032749	8292677	0	0
check_regwen_rd_A	491032749	3401	0	0
check_timeout_rd_A	491032749	3252	0	0
check_trigger_regwen_rd_A	491032749	3510	0	0
consistency_check_period_rd_A	491032749	3840	0	0
creator_sw_cfg_read_lock_rd_A	491032749	3245	0	0
direct_access_address_rd_A	491032749	3068	0	0
direct_access_wdata_0_rd_A	491032749	2046	0	0
direct_access_wdata_1_rd_A	491032749	2352	0	0
integrity_check_period_rd_A	491032749	3555	0	0
intr_enable_rd_A	491032749	4820	0	0
owner_sw_cfg_read_lock_rd_A	491032749	2966	0	0
rot_creator_auth_codesign_read_lock_rd_A	491032749	3517	0	0
rot_creator_auth_state_read_lock_rd_A	491032749	2797	0	0
vendor_test_read_lock_rd_A	491032749	2878	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491032749	8292677	0	0
T5	682046	129505	0	0
T7	97367	0	0	0
T8	0	181320	0	0
T10	14361	0	0	0
T11	26732	0	0	0
T12	49735	0	0	0
T13	0	207526	0	0
T16	30557	0	0	0
T19	0	48649	0	0
T38	28719	0	0	0
T52	12010	0	0	0
T72	13501	0	0	0
T79	13937	0	0	0
T131	0	211743	0	0
T138	0	48753	0	0
T225	0	62500	0	0
T237	0	116553	0	0
T263	0	64914	0	0
T265	0	35807	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491032749	3401	0	0
T5	682046	182	0	0
T7	97367	0	0	0
T10	14361	0	0	0
T11	26732	0	0	0
T12	49735	0	0	0
T16	30557	0	0	0
T19	0	76	0	0
T21	0	126	0	0
T23	0	44	0	0
T38	28719	0	0	0
T52	12010	0	0	0
T72	13501	0	0	0
T79	13937	0	0	0
T132	0	43	0	0
T265	0	19	0	0
T266	0	67	0	0
T335	0	41	0	0
T336	0	39	0	0
T337	0	101	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491032749	3252	0	0
T5	682046	120	0	0
T7	97367	0	0	0
T10	14361	0	0	0
T11	26732	0	0	0
T12	49735	0	0	0
T16	30557	0	0	0
T19	0	51	0	0
T21	0	176	0	0
T23	0	56	0	0
T38	28719	0	0	0
T52	12010	0	0	0
T72	13501	0	0	0
T79	13937	0	0	0
T132	0	30	0	0
T265	0	22	0	0
T266	0	32	0	0
T335	0	53	0	0
T336	0	49	0	0
T337	0	183	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491032749	3510	0	0
T5	682046	72	0	0
T7	97367	0	0	0
T10	14361	0	0	0
T11	26732	0	0	0
T12	49735	0	0	0
T16	30557	0	0	0
T19	0	74	0	0
T21	0	156	0	0
T23	0	45	0	0
T38	28719	0	0	0
T52	12010	0	0	0
T72	13501	0	0	0
T79	13937	0	0	0
T132	0	64	0	0
T265	0	17	0	0
T266	0	36	0	0
T335	0	19	0	0
T336	0	63	0	0
T337	0	139	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491032749	3840	0	0
T5	682046	107	0	0
T7	97367	0	0	0
T10	14361	0	0	0
T11	26732	0	0	0
T12	49735	0	0	0
T16	30557	0	0	0
T19	0	89	0	0
T21	0	183	0	0
T23	0	67	0	0
T38	28719	0	0	0
T52	12010	0	0	0
T72	13501	0	0	0
T79	13937	0	0	0
T132	0	25	0	0
T265	0	8	0	0
T266	0	63	0	0
T335	0	50	0	0
T336	0	44	0	0
T337	0	177	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491032749	3245	0	0
T5	682046	149	0	0
T7	97367	0	0	0
T10	14361	0	0	0
T11	26732	0	0	0
T12	49735	0	0	0
T16	30557	0	0	0
T19	0	52	0	0
T21	0	143	0	0
T23	0	39	0	0
T38	28719	0	0	0
T52	12010	0	0	0
T72	13501	0	0	0
T79	13937	0	0	0
T132	0	45	0	0
T265	0	46	0	0
T266	0	56	0	0
T335	0	22	0	0
T336	0	41	0	0
T337	0	177	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491032749	3068	0	0
T5	682046	107	0	0
T7	97367	0	0	0
T10	14361	0	0	0
T11	26732	0	0	0
T12	49735	0	0	0
T16	30557	0	0	0
T19	0	71	0	0
T21	0	205	0	0
T23	0	37	0	0
T38	28719	0	0	0
T52	12010	0	0	0
T72	13501	0	0	0
T79	13937	0	0	0
T132	0	77	0	0
T265	0	24	0	0
T266	0	50	0	0
T335	0	72	0	0
T336	0	57	0	0
T337	0	133	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491032749	2046	0	0
T5	682046	131	0	0
T7	97367	0	0	0
T10	14361	0	0	0
T11	26732	0	0	0
T12	49735	0	0	0
T16	30557	0	0	0
T19	0	41	0	0
T21	0	126	0	0
T23	0	32	0	0
T38	28719	0	0	0
T52	12010	0	0	0
T72	13501	0	0	0
T79	13937	0	0	0
T132	0	31	0	0
T265	0	19	0	0
T266	0	30	0	0
T335	0	14	0	0
T336	0	19	0	0
T337	0	134	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491032749	2352	0	0
T5	682046	154	0	0
T7	97367	0	0	0
T10	14361	0	0	0
T11	26732	0	0	0
T12	49735	0	0	0
T16	30557	0	0	0
T19	0	41	0	0
T21	0	176	0	0
T23	0	51	0	0
T38	28719	0	0	0
T52	12010	0	0	0
T72	13501	0	0	0
T79	13937	0	0	0
T132	0	42	0	0
T266	0	27	0	0
T335	0	30	0	0
T336	0	22	0	0
T337	0	137	0	0
T338	0	90	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491032749	3555	0	0
T5	682046	141	0	0
T7	97367	0	0	0
T10	14361	0	0	0
T11	26732	0	0	0
T12	49735	0	0	0
T16	30557	0	0	0
T19	0	33	0	0
T21	0	141	0	0
T23	0	37	0	0
T38	28719	0	0	0
T52	12010	0	0	0
T72	13501	0	0	0
T79	13937	0	0	0
T132	0	48	0	0
T265	0	6	0	0
T266	0	39	0	0
T335	0	38	0	0
T336	0	29	0	0
T337	0	118	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491032749	4820	0	0
T5	682046	87	0	0
T7	97367	0	0	0
T10	14361	0	0	0
T11	26732	0	0	0
T12	49735	0	0	0
T16	30557	0	0	0
T19	0	85	0	0
T21	0	186	0	0
T38	28719	0	0	0
T52	12010	0	0	0
T72	13501	0	0	0
T79	13937	0	0	0
T132	0	36	0	0
T194	0	17	0	0
T222	0	34	0	0
T265	0	42	0	0
T266	0	53	0	0
T335	0	34	0	0
T336	0	77	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491032749	2966	0	0
T5	682046	147	0	0
T7	97367	0	0	0
T10	14361	0	0	0
T11	26732	0	0	0
T12	49735	0	0	0
T16	30557	0	0	0
T19	0	79	0	0
T21	0	177	0	0
T23	0	50	0	0
T38	28719	0	0	0
T52	12010	0	0	0
T72	13501	0	0	0
T79	13937	0	0	0
T132	0	33	0	0
T265	0	23	0	0
T266	0	81	0	0
T335	0	57	0	0
T336	0	47	0	0
T337	0	117	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491032749	3517	0	0
T5	682046	145	0	0
T7	97367	0	0	0
T10	14361	0	0	0
T11	26732	0	0	0
T12	49735	0	0	0
T16	30557	0	0	0
T19	0	53	0	0
T21	0	171	0	0
T23	0	49	0	0
T38	28719	0	0	0
T52	12010	0	0	0
T72	13501	0	0	0
T79	13937	0	0	0
T132	0	54	0	0
T265	0	46	0	0
T266	0	39	0	0
T335	0	67	0	0
T336	0	35	0	0
T337	0	183	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491032749	2797	0	0
T5	682046	103	0	0
T7	97367	0	0	0
T10	14361	0	0	0
T11	26732	0	0	0
T12	49735	0	0	0
T16	30557	0	0	0
T19	0	61	0	0
T21	0	142	0	0
T23	0	23	0	0
T38	28719	0	0	0
T52	12010	0	0	0
T72	13501	0	0	0
T79	13937	0	0	0
T132	0	58	0	0
T265	0	29	0	0
T266	0	54	0	0
T335	0	58	0	0
T336	0	49	0	0
T337	0	117	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491032749	2878	0	0
T5	682046	110	0	0
T7	97367	0	0	0
T10	14361	0	0	0
T11	26732	0	0	0
T12	49735	0	0	0
T16	30557	0	0	0
T19	0	18	0	0
T21	0	160	0	0
T23	0	34	0	0
T38	28719	0	0	0
T52	12010	0	0	0
T72	13501	0	0	0
T79	13937	0	0	0
T132	0	31	0	0
T265	0	25	0	0
T266	0	32	0	0
T335	0	45	0	0
T336	0	44	0	0
T337	0	115	0	0