Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_part_sel_idx

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
74.55 65.65 89.83 88.89 53.85


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
74.55 65.65 89.83 88.89 53.85


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.34 94.81 96.15 97.14 96.43 97.18 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_otp_ctrl_dai.u_part_sel_idx

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
74.55 65.65 89.83 88.89 53.85


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
74.55 65.65 89.83 88.89 53.85


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.68 95.88 95.06 82.46 90.00 100.00 u_otp_ctrl_dai


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_arbiter_fixed
Line No.TotalCoveredPercent
TOTAL1318665.65
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN97100.00
CONT_ASSIGN97100.00
CONT_ASSIGN97100.00
CONT_ASSIGN97100.00
CONT_ASSIGN97100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS105600.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS105600.00
ALWAYS105600.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 11 11
87 0 11
89 0 11
97 0 5
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 0 1
107 0 1
109 0 1
110 0 1
112 0 1
113 0 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 0 1
107 0 1
109 0 1
110 0 1
112 0 1
113 0 1
105 0 1
107 0 1
109 0 1
110 0 1
112 0 1
113 0 1
124 1 1
128 1 1
129 1 1
132 unreachable


Cond Coverage for Module : prim_arbiter_fixed
TotalCoveredPercent
Conditions11910689.08
Logical11910689.08
Non-Logical00
Event00

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00Not Covered
01CoveredT1,T2,T6
10CoveredT1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T6
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T6

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T7,T8
10CoveredT1,T2,T6

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00Not Covered
01Unreachable
10Unreachable

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[3].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[3].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[4].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[4].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T6

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT5,T7,T8

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00Not Covered
01Unreachable
10Unreachable

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[7].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[7].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00Not Covered
01Unreachable
10Unreachable

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])
-1-StatusTests
0Unreachable
1Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[3].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[4].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])
-1-StatusTests
0CoveredT5,T7,T8
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])
-1-StatusTests
0Unreachable
1Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[7].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])
-1-StatusTests
0Unreachable
1Not Covered

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T6

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])
-1-StatusTests
0Unreachable
1Not Covered

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[3].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[4].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])
-1-StatusTests
0CoveredT5,T7,T8
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])
-1-StatusTests
0Unreachable
1Not Covered

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[7].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])
-1-StatusTests
0Unreachable
1Not Covered

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T6
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T6
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T4
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T6
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT5,T7,T8
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[7].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T6
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[7].Pa] & gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

Branch Coverage for Module : prim_arbiter_fixed
Line No.TotalCoveredPercent
Branches 54 48 88.89
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 1 0 0.00
TERNARY 110 1 0 0.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 1 0 0.00
TERNARY 110 1 0 0.00
TERNARY 109 1 0 0.00
TERNARY 110 1 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T6


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T6


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T6


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T6


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T6


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T6


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T7,T8


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T7,T8


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable


Assert Coverage for Module : prim_arbiter_fixed
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 7 53.85
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 7 53.85




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 976015500 974324144 0 0
CheckNGreaterZero_A 2306 2306 0 0
GntImpliesReady_A 976015500 0 0 0
GntImpliesValid_A 976015500 0 0 0
GrantKnown_A 976015500 974324144 0 0
IdxKnown_A 976015500 974324144 0 0
IndexIsCorrect_A 976015500 0 0 0
NoReadyValidNoGrant_A 976015500 0 0 0
Priority_A 976015500 974324144 0 0
ReadyAndValidImplyGrant_A 976015500 0 0 0
ReqAndReadyImplyGrant_A 976015500 0 0 0
ReqImpliesValid_A 976015500 974324144 0 0
ValidKnown_A 976015500 974324144 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976015500 974324144 0 0
T1 74102 73644 0 0
T2 49770 49176 0 0
T3 50996 49866 0 0
T4 170670 167736 0 0
T5 1364092 1364072 0 0
T6 34186 33658 0 0
T9 165044 164732 0 0
T10 28722 28176 0 0
T11 53464 52612 0 0
T12 99470 98532 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2306 2306 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T6 2 2 0 0
T9 2 2 0 0
T10 2 2 0 0
T11 2 2 0 0
T12 2 2 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976015500 0 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976015500 0 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976015500 974324144 0 0
T1 74102 73644 0 0
T2 49770 49176 0 0
T3 50996 49866 0 0
T4 170670 167736 0 0
T5 1364092 1364072 0 0
T6 34186 33658 0 0
T9 165044 164732 0 0
T10 28722 28176 0 0
T11 53464 52612 0 0
T12 99470 98532 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976015500 974324144 0 0
T1 74102 73644 0 0
T2 49770 49176 0 0
T3 50996 49866 0 0
T4 170670 167736 0 0
T5 1364092 1364072 0 0
T6 34186 33658 0 0
T9 165044 164732 0 0
T10 28722 28176 0 0
T11 53464 52612 0 0
T12 99470 98532 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976015500 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976015500 0 0 0

Priority_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976015500 974324144 0 0
T1 74102 73644 0 0
T2 49770 49176 0 0
T3 50996 49866 0 0
T4 170670 167736 0 0
T5 1364092 1364072 0 0
T6 34186 33658 0 0
T9 165044 164732 0 0
T10 28722 28176 0 0
T11 53464 52612 0 0
T12 99470 98532 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976015500 0 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976015500 0 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976015500 974324144 0 0
T1 74102 73644 0 0
T2 49770 49176 0 0
T3 50996 49866 0 0
T4 170670 167736 0 0
T5 1364092 1364072 0 0
T6 34186 33658 0 0
T9 165044 164732 0 0
T10 28722 28176 0 0
T11 53464 52612 0 0
T12 99470 98532 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 976015500 974324144 0 0
T1 74102 73644 0 0
T2 49770 49176 0 0
T3 50996 49866 0 0
T4 170670 167736 0 0
T5 1364092 1364072 0 0
T6 34186 33658 0 0
T9 165044 164732 0 0
T10 28722 28176 0 0
T11 53464 52612 0 0
T12 99470 98532 0 0

Line Coverage for Instance : tb.dut.u_part_sel_idx
Line No.TotalCoveredPercent
TOTAL1318665.65
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN97100.00
CONT_ASSIGN97100.00
CONT_ASSIGN97100.00
CONT_ASSIGN97100.00
CONT_ASSIGN97100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS105600.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS105600.00
ALWAYS105600.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 11 11
87 0 11
89 0 11
97 0 5
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 0 1
107 0 1
109 0 1
110 0 1
112 0 1
113 0 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 0 1
107 0 1
109 0 1
110 0 1
112 0 1
113 0 1
105 0 1
107 0 1
109 0 1
110 0 1
112 0 1
113 0 1
124 1 1
128 1 1
129 1 1
132 unreachable


Cond Coverage for Instance : tb.dut.u_part_sel_idx
TotalCoveredPercent
Conditions11810689.83
Logical11810689.83
Non-Logical00
Event00

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTestsExclude Annotation
00Excluded vcs_gen_start:level=0,offset=0:vcs_gen_end:VC_COV_UNR
01CoveredT5,T8,T13
10CoveredT1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT5,T8,T13
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT5,T8,T13

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T8,T13
10CoveredT1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T8,T13
10CoveredT5,T8,T13

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00Not Covered
01Unreachable
10Unreachable

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T8,T13
10CoveredT1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[3].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[3].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T8,T13
10CoveredT5,T8,T13

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[4].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[4].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T8,T13
10CoveredT5,T8,T13

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT5,T8,T13

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00Not Covered
01Unreachable
10Unreachable

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[7].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[7].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00Not Covered
01Unreachable
10Unreachable

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T13

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT5,T8,T13
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])
-1-StatusTests
0CoveredT5,T8,T13
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])
-1-StatusTests
0Unreachable
1Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[3].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])
-1-StatusTests
0CoveredT5,T8,T13
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[4].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])
-1-StatusTests
0CoveredT5,T8,T13
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])
-1-StatusTests
0CoveredT5,T8,T13
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])
-1-StatusTests
0Unreachable
1Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[7].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])
-1-StatusTests
0Unreachable
1Not Covered

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T8,T13

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT5,T8,T13
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])
-1-StatusTests
0CoveredT5,T8,T13
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])
-1-StatusTests
0Unreachable
1Not Covered

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[3].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])
-1-StatusTests
0CoveredT5,T8,T13
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[4].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])
-1-StatusTests
0CoveredT5,T8,T13
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])
-1-StatusTests
0CoveredT5,T8,T13
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])
-1-StatusTests
0Unreachable
1Not Covered

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[7].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])
-1-StatusTests
0Unreachable
1Not Covered

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT5,T8,T13
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT5,T8,T13
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT5,T8,T13
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT5,T8,T13
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT5,T8,T13
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[7].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT5,T8,T13
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[7].Pa] & gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

Branch Coverage for Instance : tb.dut.u_part_sel_idx
Line No.TotalCoveredPercent
Branches 54 48 88.89
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 1 0 0.00
TERNARY 110 1 0 0.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 1 0 0.00
TERNARY 110 1 0 0.00
TERNARY 109 1 0 0.00
TERNARY 110 1 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T5,T8,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T5,T8,T13
0 Covered T1,T2,T3


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T13


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T13


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T13


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T13


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T13


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T13


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T13


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T13


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T13


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T13


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable


Assert Coverage for Instance : tb.dut.u_part_sel_idx
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 7 53.85
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 7 53.85




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 488007750 487162072 0 0
CheckNGreaterZero_A 1153 1153 0 0
GntImpliesReady_A 488007750 0 0 0
GntImpliesValid_A 488007750 0 0 0
GrantKnown_A 488007750 487162072 0 0
IdxKnown_A 488007750 487162072 0 0
IndexIsCorrect_A 488007750 0 0 0
NoReadyValidNoGrant_A 488007750 0 0 0
Priority_A 488007750 487162072 0 0
ReadyAndValidImplyGrant_A 488007750 0 0 0
ReqAndReadyImplyGrant_A 488007750 0 0 0
ReqImpliesValid_A 488007750 487162072 0 0
ValidKnown_A 488007750 487162072 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 487162072 0 0
T1 37051 36822 0 0
T2 24885 24588 0 0
T3 25498 24933 0 0
T4 85335 83868 0 0
T5 682046 682036 0 0
T6 17093 16829 0 0
T9 82522 82366 0 0
T10 14361 14088 0 0
T11 26732 26306 0 0
T12 49735 49266 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 0 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 0 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 487162072 0 0
T1 37051 36822 0 0
T2 24885 24588 0 0
T3 25498 24933 0 0
T4 85335 83868 0 0
T5 682046 682036 0 0
T6 17093 16829 0 0
T9 82522 82366 0 0
T10 14361 14088 0 0
T11 26732 26306 0 0
T12 49735 49266 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 487162072 0 0
T1 37051 36822 0 0
T2 24885 24588 0 0
T3 25498 24933 0 0
T4 85335 83868 0 0
T5 682046 682036 0 0
T6 17093 16829 0 0
T9 82522 82366 0 0
T10 14361 14088 0 0
T11 26732 26306 0 0
T12 49735 49266 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 0 0 0

Priority_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 487162072 0 0
T1 37051 36822 0 0
T2 24885 24588 0 0
T3 25498 24933 0 0
T4 85335 83868 0 0
T5 682046 682036 0 0
T6 17093 16829 0 0
T9 82522 82366 0 0
T10 14361 14088 0 0
T11 26732 26306 0 0
T12 49735 49266 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 0 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 0 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 487162072 0 0
T1 37051 36822 0 0
T2 24885 24588 0 0
T3 25498 24933 0 0
T4 85335 83868 0 0
T5 682046 682036 0 0
T6 17093 16829 0 0
T9 82522 82366 0 0
T10 14361 14088 0 0
T11 26732 26306 0 0
T12 49735 49266 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 487162072 0 0
T1 37051 36822 0 0
T2 24885 24588 0 0
T3 25498 24933 0 0
T4 85335 83868 0 0
T5 682046 682036 0 0
T6 17093 16829 0 0
T9 82522 82366 0 0
T10 14361 14088 0 0
T11 26732 26306 0 0
T12 49735 49266 0 0

Line Coverage for Instance : tb.dut.u_otp_ctrl_dai.u_part_sel_idx
Line No.TotalCoveredPercent
TOTAL1318665.65
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN87100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN89100.00
CONT_ASSIGN97100.00
CONT_ASSIGN97100.00
CONT_ASSIGN97100.00
CONT_ASSIGN97100.00
CONT_ASSIGN97100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS105600.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS10566100.00
ALWAYS105600.00
ALWAYS105600.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13200
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
85 11 11
87 0 11
89 0 11
97 0 5
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 0 1
107 0 1
109 0 1
110 0 1
112 0 1
113 0 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 1 1
107 1 1
109 1 1
110 1 1
112 1 1
113 1 1
105 0 1
107 0 1
109 0 1
110 0 1
112 0 1
113 0 1
105 0 1
107 0 1
109 0 1
110 0 1
112 0 1
113 0 1
124 1 1
128 1 1
129 1 1
132 unreachable


Cond Coverage for Instance : tb.dut.u_otp_ctrl_dai.u_part_sel_idx
TotalCoveredPercent
Conditions11810689.83
Logical11810689.83
Non-Logical00
Event00

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTestsExclude Annotation
00Excluded vcs_gen_start:level=0,offset=0:vcs_gen_end:VC_COV_UNR
01CoveredT1,T2,T6
10CoveredT1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T6
01CoveredT1,T2,T9
10CoveredT1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T6

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T6
01CoveredT1,T2,T6
10CoveredT1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T9

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[2].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT7,T8,T14
10CoveredT1,T2,T6

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[3].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00Not Covered
01Unreachable
10Unreachable

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T6
01CoveredT1,T2,T4
10CoveredT1,T2,T3

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T6

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T9

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[3].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[3].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T4

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[4].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[4].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10CoveredT1,T2,T6

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT7,T8,T14

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00Not Covered
01Unreachable
10Unreachable

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[7].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[7].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------
-1--2-StatusTests
00Not Covered
01Unreachable
10Unreachable

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T9
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])
-1-StatusTests
0Unreachable
1Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])
-1-StatusTests
0CoveredT1,T2,T9
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[3].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[4].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])
-1-StatusTests
0CoveredT7,T8,T14
1CoveredT1,T2,T3

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])
-1-StatusTests
0Unreachable
1Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[7].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])
-1-StatusTests
0Unreachable
1Not Covered

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T6

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T6

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T6

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T9
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[2].C0])
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[3].C0])
-1-StatusTests
0Unreachable
1Not Covered

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T6

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])
-1-StatusTests
0CoveredT1,T2,T9
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[3].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[3].C0])
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[4].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[4].C0])
-1-StatusTests
0CoveredT1,T2,T6
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])
-1-StatusTests
0CoveredT7,T8,T14
1CoveredT1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])
-1-StatusTests
0Unreachable
1Not Covered

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[7].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[7].C0])
-1-StatusTests
0Unreachable
1Not Covered

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T6
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T9
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T6
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T6
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T9
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T4
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T6
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT7,T8,T14
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10Unreachable
11Unreachable

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[7].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------
-1--2-StatusTests
01Unreachable
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T6
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T6
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[1].gen_level[1].Pa] & gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T6
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] & gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[2].Pa] & gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[2].gen_level[3].Pa] & gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T6
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[3].gen_level[7].Pa] & gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------
-1--2-StatusTests
01Not Covered
10Unreachable
11Unreachable

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11Unreachable

Branch Coverage for Instance : tb.dut.u_otp_ctrl_dai.u_part_sel_idx
Line No.TotalCoveredPercent
Branches 54 48 88.89
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 1 0 0.00
TERNARY 110 1 0 0.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 2 2 100.00
TERNARY 110 2 2 100.00
TERNARY 109 1 0 0.00
TERNARY 110 1 0 0.00
TERNARY 109 1 0 0.00
TERNARY 110 1 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T6


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[1].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T6


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T9


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[2].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T9


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T6


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[2].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T6


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[2].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T6


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T6


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T9


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T9


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[3].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T6


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[4].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T6


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T7,T8,T14


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T7,T8,T14


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable


LineNo. Expression -1-: 109 (gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable


LineNo. Expression -1-: 110 (gen_normal_case.gen_tree[3].gen_level[7].gen_nodes.sel) ?

Branches:
-1-StatusTests
1 Not Covered
0 Unreachable


Assert Coverage for Instance : tb.dut.u_otp_ctrl_dai.u_part_sel_idx
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 7 53.85
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 7 53.85




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckHotOne_A 488007750 487162072 0 0
CheckNGreaterZero_A 1153 1153 0 0
GntImpliesReady_A 488007750 0 0 0
GntImpliesValid_A 488007750 0 0 0
GrantKnown_A 488007750 487162072 0 0
IdxKnown_A 488007750 487162072 0 0
IndexIsCorrect_A 488007750 0 0 0
NoReadyValidNoGrant_A 488007750 0 0 0
Priority_A 488007750 487162072 0 0
ReadyAndValidImplyGrant_A 488007750 0 0 0
ReqAndReadyImplyGrant_A 488007750 0 0 0
ReqImpliesValid_A 488007750 487162072 0 0
ValidKnown_A 488007750 487162072 0 0


CheckHotOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 487162072 0 0
T1 37051 36822 0 0
T2 24885 24588 0 0
T3 25498 24933 0 0
T4 85335 83868 0 0
T5 682046 682036 0 0
T6 17093 16829 0 0
T9 82522 82366 0 0
T10 14361 14088 0 0
T11 26732 26306 0 0
T12 49735 49266 0 0

CheckNGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1153 1153 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

GntImpliesReady_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 0 0 0

GntImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 0 0 0

GrantKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 487162072 0 0
T1 37051 36822 0 0
T2 24885 24588 0 0
T3 25498 24933 0 0
T4 85335 83868 0 0
T5 682046 682036 0 0
T6 17093 16829 0 0
T9 82522 82366 0 0
T10 14361 14088 0 0
T11 26732 26306 0 0
T12 49735 49266 0 0

IdxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 487162072 0 0
T1 37051 36822 0 0
T2 24885 24588 0 0
T3 25498 24933 0 0
T4 85335 83868 0 0
T5 682046 682036 0 0
T6 17093 16829 0 0
T9 82522 82366 0 0
T10 14361 14088 0 0
T11 26732 26306 0 0
T12 49735 49266 0 0

IndexIsCorrect_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 0 0 0

NoReadyValidNoGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 0 0 0

Priority_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 487162072 0 0
T1 37051 36822 0 0
T2 24885 24588 0 0
T3 25498 24933 0 0
T4 85335 83868 0 0
T5 682046 682036 0 0
T6 17093 16829 0 0
T9 82522 82366 0 0
T10 14361 14088 0 0
T11 26732 26306 0 0
T12 49735 49266 0 0

ReadyAndValidImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 0 0 0

ReqAndReadyImplyGrant_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 0 0 0

ReqImpliesValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 487162072 0 0
T1 37051 36822 0 0
T2 24885 24588 0 0
T3 25498 24933 0 0
T4 85335 83868 0 0
T5 682046 682036 0 0
T6 17093 16829 0 0
T9 82522 82366 0 0
T10 14361 14088 0 0
T11 26732 26306 0 0
T12 49735 49266 0 0

ValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 488007750 487162072 0 0
T1 37051 36822 0 0
T2 24885 24588 0 0
T3 25498 24933 0 0
T4 85335 83868 0 0
T5 682046 682036 0 0
T6 17093 16829 0 0
T9 82522 82366 0 0
T10 14361 14088 0 0
T11 26732 26306 0 0
T12 49735 49266 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%