Module : prim_reg_we_check
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_reg_we_check_0/rtl/prim_reg_we_check.sv
Module self-instances :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| tb.dut.u_reg_core.u_prim_reg_we_check | |||||||
| tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check |
Module Instance : tb.dut.u_reg_core.u_prim_reg_we_check
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 98.65 | 100.00 | 94.59 | 100.00 | 100.00 | u_reg_core |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_prim_buf | 100.00 | 100.00 | |||||
| u_prim_onehot_check | 100.00 | 100.00 |
Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | u_reg_top |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_prim_buf | 100.00 | 100.00 | |||||
| u_prim_onehot_check | 100.00 | 100.00 |