Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25222051

1

T1

5624

T2

2375

T3

70

full_word

8375464

1

T1

4176

T2

1271

T3

24

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33597225	1			T1	9800		T2	3646		T3	94
auto[TlIntgErrCmd]	92	1			T248	2		T249	3		T250	5
auto[TlIntgErrData]	104	1			T248	2		T249	3		T250	11
auto[TlIntgErrBoth]	94	1			T248	6		T249	4		T250	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9905341

1

T1

8763

T2

3347

T3

1

auto[1]

23692174

1

T1

1037

T2

299

T3

93

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6218847	1			T1	4942		T2	2193		T3	1
auto[TlIntgErrNone]	partial	auto[1]	19002940	1			T1	682		T2	182		T3	69
auto[TlIntgErrNone]	full_word	auto[0]	3686366	1			T1	3821		T2	1154		T4	334
auto[TlIntgErrNone]	full_word	auto[1]	4689072	1			T1	355		T2	117		T3	24
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T248	1		T249	2		T250	1
auto[TlIntgErrCmd]	partial	auto[1]	40	1			T249	1		T250	2		T257	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T250	1		T327	1		T323	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T248	1		T250	1		T257	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T248	2		T249	1		T250	4
auto[TlIntgErrData]	partial	auto[1]	55	1			T249	2		T250	7		T257	6
auto[TlIntgErrData]	full_word	auto[0]	3	1			T257	1		T256	1		T328	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T328	1		T323	1		T324	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T248	2		T249	1		T250	3
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T248	4		T249	3		T250	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T325	1		T327	1		T328	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T326	1		T321	1		T328	1